User manual

Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 292
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
• Efficient transaction scheduling to optimize data bandwidth and latency
• Advanced re-ordering engine to maximize memory access efficiency for continuous reads and
writes as well as random reads and writes
• Write - read address collision detection to avoid data corruption
• Obeys AXI ordering rules
10.1.2 Block Diagram
The block diagram for the DDR memory controller is shown in Figure 10-1. The DDR memory
controller consists of an arbiter, a core with transaction scheduler, and the physical sequencing of the
DDR memory signals.
The controller core and transaction scheduler contains two 32-entry CAMs to perform DDR data
service re-ordering to maximize DDR memory access efficiency. It also contains a fly-by channel for
low latency access to DDR memory without going through the CAM.
The PHY processes read/write requests from the controller and translates them into specific signals
within the timing constraints of the target DDR memory. Signals from the controller are used by the
PHY to produce internal signals that connect to the pads of the PS using the PHY. The pads connect
directly, via the PCB signal traces, to the external memory devices.
The arbiter arbitrates across the four AXI ports for access to the DDR core. The arbitration is priority
based and also allows promotion of priorities via an urgent mechanism.
X-Ref Target - Figure 10-1
Figure 10-1: DDR Memory Controller Block Diagram
UG585_c10_01_120913
DDR Interface
Configuration
Registers
CPUs
and ACP
• AXI 3 Port Arbiter
• Seperate Read/Write Requests
DDR Core
• Transaction Scheduler and Queues
• Programmable Algorithms
DDR PHY
• DDR2, LPDDR2, DDR3, DDR3L
DDR DRAM Memory Device(s)
S0
64-bit
Other Bus
Masters
S1
64-bit
AXI_
HP{2,3}
S2
64-bit
16 or 32-bit
AXI_
HP{1,0}
S3 S
64-bit 32-bit
APB
Device Boundary