User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 299
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
10.3.1 Row/Bank/Column Address Mapping
The DDRC is responsible for mapping byte-addressable physical addresses used by the PS and PL AXI
masters to DDR row, bank and column addresses. This address mapping has a limited configurability
to allow user optimization. Optimizing the mapping to specific data access patterns can allow
increased DDR utilization by reducing page and row change overhead.
Note: Many combinations of address remapping are not available, notably a complete
bank-row-column mapping.
The address mapper associates linear request addresses to DRAM addresses by selecting the AXI bit
that maps to each and every applicable DRAM address bit. The full available address space is only
accessible to the user when no two DRAM address bits are determined by the same AXI address bit.
Each DRAM row, bank, and column address bit has an associated register vector to determine its
associated AXI source in the DDRC DRAM_addr_map_bank, DRAM_addr_map_row, and
DRAM_addr_map_col registers. The associated AXI address bit is determined by adding the internal
base of a given register to the programmed value for that register, as described in the following
equation:
[internal base] + [register value] = [AXI address bit number]
For example, from the description for reg_ddrc_addrmap_col_b3, it can be seen that this register
determines the mapping for DRAM column bit 4 and its internal base is 3. When the full data bus is
in use, DRAM column bit 4 is determined by the following:
[internal base] + [register value].
If reg_ddrc_addrmap_col_b3 register is programmed to 2, then the AXI address bit is:
3 + 2 = 5.
In other words, the column address bit 4 sent to DRAM is mapped to AXI address bit *_ADDR[5].
All the column bits left-shift one bit in half bus width mode (including ECC). In this case,
reg_ddrc_addrmap_col_b2 determines the mapping of DRAM column address bit 4. In the full bus
width case, reg_ddrc_addrmap_col_b3 determines DRAM column address 4.
10.4 DDRC Arbitration
The DDRC arbitration consists of three stages (see Figure 10-5):
•Stage 1 is AXI read/write port arbitration
• Stage 2 is winner of read and write compete
• Stage 3 is transaction scheduler
Each of these stages has their own arbitration steps that will be discussed in more detail.