User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 3
UG585 (v1.11) September 27, 2016
08/08/2012 1.2
(Cont’d)
Reorganized, clarified, and expanded Chapter 19 to include programming models
(added sections 19.1.3 Notices, 19.3 Programming Guide, and 19.5.1 MIO
Programming). Updated Table 22-2 and Table 22-3 in Chapter 22. Added section CPU
Clock Divisor Restriction in Chapter 25. Updated Table 26-4 in Chapter 26. Clarified
section 27.3 I/O Signals in Chapter 27. Added section 28.1.2 Notices in Chapter 28.
Clarified Mapping Summary and updated Table 29-1, Table 29-3, and Table 29-5 in
Chapter 29. Added section 30.1.3 Notices in Chapter 30. Updated data sheet references
in section A.3.1 Zynq-7000 AP SoC Documents of Appendix A. Updated register
database in sections B.3 Module Summary through B.34 USB Controller (usb) in
Appendix B.
10/30/2012 1.3 Changed product name from Extensible Processing Platform (EPP) to All Programmable
SoC (AP SoC) throughout document. Added Table 1-1. Added 2.1.1 Notices, 2.4 PS–PL
Voltage Level Shifter Enables, A summary of the dedicated PS signal pins is shown in
Table 2-2., VREF Source Considerations, updated Table 2-2, and added warning to
2.5.7 MIO Pin Electrical Parameters. Added Initialization of L1 Caches, 3.2.4 Memory
Ordering, expanded 3.2.5 Memory Management Unit (MMU), added Cache Lockdown
by Way Sequence and 3.9 CPU Initialization Sequence. Added 7z007s and 7z010 Device
Notice and expanded Table 4-7. Updated and expanded tables in 6
.3.4 Quad-SPI Boot
through 6.3.13 Post BootROM State, reworked 6.3.6 Debug Status, and added
6.3.13 Post BootROM State and AXI and DMA Done Status Interrupts. Reworked
Table 7-4. Added 8.1.2 Notices, Interrupt to PS Interrupt Controller, and Reset.
Reorganized and expanded Chapter 9, DMA Controller. Added 10.1.3 Notices,
expanded 10.1.6 I/O Signals, added 10.6.11 DRAM Write Latency Restriction,
10.8.1 ECC Initialization, 10.8.4 ECC Programming Model, and 10.9.1 Operating Modes.
Added 12.2.4 I/O Mode Considerations and updated 12.3.5 Rx/Tx FIFO Response to I/O
Command Sequences. Reworked 16.3.3 I/O Configuration, added 16.4 IEEE 1588 Time
Stamping and 16.6.7 MIO Pin Considerations. Added 18.2.7 CAN0-to-CAN1
Connection. Expanded 19.1 Introduction, 19.1.3 Notices, and Table 19-1. Added
Receiver Timeout Mechanism, updated Figure 19-7. Added 19.2.9 UART0-to-UART1
Connection and 19.2.10 Status and Interrupts, expanded 19.2.11 Modem Control,
reworked 19.3 Programming Guide and 19.4.2 Resets. Added 20.2.7 I2C0-to-I2C1
Connection. Added 21.1.2 PL Resources by Device Type, Voltage Level Shifters and
reorganized content of Chapter 21, Programmable Logic Description. Added
25.7.1 Clock Throttle. Expanded 26.4.1 PL General Purpose User Resets. Updated
register database in sections B.3 Module Summary through B.34 USB Controller (usb)
in Appendix B.
11/16/2012 1.4 Changed second bullet under NAND Flash Interface from “
Up to a 4 GB device” to “Up
to a 1 GB device” in
Chapter 11, Static Memory Controller.
Date Version Revision