User manual

Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 306
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
Inside the controller, assertion of this signal causes the state machine to switch from one state to
another. For example, if the DDRC is currently servicing reads and co_gs_go2critical_wr goes High,
the controller ignores the normal state switching methods (starvation counter etc), and jumps to
servicing writes. There is a register in the controller to control how long to keep servicing the current
command type before switching to the other (reg_ddrc_go2critical_hysteresis field in the DDRC
ctrl_reg2).
In summary, this go2critical feature is used in the controller and ensures fast switching between
reads and writes for transactions with super high priority.
Note:
1. The normal programming condition is expected to be reg_ddrc_prefer_Write=0. (this is a bit field
in the DRAM_param_reg4 register) This means that the read requests are always serviced
immediately when received by an idle controller. Also, it is often desirable to set the
reg_ddrc_rdwr_idle_gap (this field is in the ddrc_ctrl register) to a very low number (such as 0, 1,
or 2) to ensure that writes do not go un-serviced in an otherwise-idle controller for any length of
time, wasting bandwidth. (The trade-off here is that by servicing writes more quickly, the
likelihood increases that reads issued to the controller immediately following writes incurs
additional latency to allow writes to be serviced and turn the bus around.)
2. Because the ordering is guaranteed on all requests issued to the controller, write latency must
not be a concern to system design. (In the event that write data is required by a subsequent read,
the controller automatically forces the write data out to DRAM before servicing the read.)
10.4.8 Read Priority Management
Normally in a read mode, high priority read requests are preferred for service over low priority read
requests. However, if the low priority read transaction store is critical and the high priority read
transaction store is not, then low priority read requests are preferred over high priority read requests.
This prevents starvation of low priority reads.
10.4.9 Write Combine
The write combine feature allow multiple writes to the same address to be combined into a single
write to DRAM. When a new write collides with a queued write in the CAM:
• If write combine is enabled, the DDRC overwrites the data for the old write with that from the
new write and only performs one write transaction (write combine).
• If write combine is disabled, the DDRC follows the following sequence of operations:
°
Holds the new write transaction in a temporary buffer
°
Applies flow control back to the core to prevent more transactions from arriving
°
Flushes the internal queue holding the colliding transaction until that transaction has been
serviced
°
Accepts the new transaction and removes flow control