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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 307
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
10.4.10 Credit Mechanism
The DRAM controller employs a credit mechanism to ensure that buffers do not overflow (pending
DDR transactions). The interface making the request to the controller can only request commands
for which it has been granted credits or open slots in the queues to issue.
Credits are tracked separately for the following three command types:
• High priority reads
• Low priority reads
•Writes
Credits are counted for each command type independently according to the following rules:
• Initially the interface has zero credits.
• Following the de-assertion of reset to the DRAM controller, credits are issued to the interface
for each command type. A given credit count increments every time a credit is issued by the
DRAM controller, indicated by the assertion of the appropriate *_credit signal on the rising edge
of the clock.
• When the credit count is greater than zero, the interface can issue requests of that type to the
controller. Each time a request is issued to the controller, the associated credit count is
decremented.
10.5 Controller PHY (DDRP)
The DDRP processes read and write requests from the DDRC and translates them into specific signals
within the timing constraints of the target DDR memory. The DDRP is composed of functional units
including PHY control, master DLL, and read/write leveling logic. The PHY data slice block handles
the DQ, DM, DQS, DQ_OE and DQS_OE signals. The PHY control block synchronizes all of the control
signals with the DDR_x3 clock.
There are two kinds of DLLs, the master DLL, and the slave DLL. The DLLs are responsible for creating
the precise timing windows required by the DDR memories to read and write data. The master DLL
measures the cycle period in terms of a number of taps and passes this number through the ratio
logic to the slave DLLs. The slave DLLs can be separated on the target die to minimize skew and delay
and to account for process, temperature and voltage variations.
Write leveling and read leveling are new functions required for DDR3, DDR3L operation. These
functions help automatically determine delay timings required to align data to the optimal window
for reliable data capture:
• Read leveling and write leveling for DDR3, DDR3L
• Support for 16- and 32-bit data bus width with one rank
• Optional ECC with a 16-bit data width
• Individual bytes with read data mask bits