User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 309
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
Programming the DDR clock involves the DDR_PLL_CTRL and DDR_CLK_CTRL registers in the SLCR.
Please refer to section 25.10.4 PLLs in Chapter 25, for DDR PLL programming.
In addition to the main DDR clock, a 10 MHz clock is used by the digitally controlled impedance (DCI)
function built into the DDR IOB. This clock is configured via the SLCR DCI_CLK_CTRL register.
10.6.2 DDR IOB Impedance Calibration
The DDR IOBs support calibrated drive strength and termination strength using the DCI digitally
controlled impedance mode of the IOB. In DDR2/DDR3/DDR3L modes this is used to calibrate
termination strength. In LPDDR2 mode this is used to calibrate drive strength. The DCI state machine
requires two external pins, VRN and VRP, which are connected to external resistors to V
CCO_DDR
and
ground, respectively. DCI settings are shown in Table 10-6.
When enabled, the DCI state machine will automatically match drive and termination impedance to
the external resistors. This background calibration takes 1-2 ms to lock and then runs continuously.
Calibration
1. Configure the clock module to configure a 10 MHz clock on dci_clk
2. Enable the DDR DCI calibration system using the SLCR registers DDRIOB_DCI_CTRL and
DDRIOB_DCI_STATUS
a. Toggle DDRIOB_DCI_CTRL.RESET_B to 0 and set to 1
b. Set DDRIOB_DCI_CTRL.PREF_OPT, and NREF_OPT fields according to Table 10-7
c. Set DDRIOB_DCI_CTRL. UPDATE_CONTROL to 0
d. Set DDRIOB_DCI_CTRL.ENABLE to 1
e. Poll on the DDRIOB_DCI_STATUS.DONE bit until it is 1
Table 10-6: DCI Settings
DDR standard
Ter minat ion
Impedance
Drive Impedance
VRN resistor
(to V
CCO_DDR
)
VRP resistor
(to ground)
DDR3/DDR3L 40Ω N/A 80Ω 80Ω
DDR2 50Ω N/A 100Ω 100Ω
LPDDR2 None 40Ω 40Ω 40Ω
Table 10-7: Calibration
Field Name Reset
Power
Down
DCI Enable
DDR3/DDR3L
DCI Enable
DDR2
DCI Enable
LPDDR2
DCI Disabled
UPDATE_CONTROL 00 0 0 0 1
PREF_OPT2[2:0] 000 000 000 000 000 000
PREF_OPT1[1:0] 00 00 00 00 10 00
NREF_OPT4[2:0] 000 000 001 001 001 000
NREF_OPT2[2:0] 000 000 000 000 000 000
NREF_OPT1[1:0] 00 00 00 00 10 00