User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 311
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
4. Set TERM_DISABLE_MODE and IBUF_DISABLE_MODE to enable power saving input modes. The
TERM_DISABLE_MODE and IBUF_DISABLE_MODE fields should not be set before DDR training
has completed.
5. Set INP_TYPE to V
REF
based differential receiver for SSTL, HSTL for single ended inputs.
6. Set INP_TYPE to Differential input receiver for differential inputs.
7. Set TERM_EN to enabled for DDR3/DDR32L and DDR2 bidirectional I/Os (Outputs and LPRDDR2
IOs are not terminated).
8. Set DDRIOB_DATA1 and DDRIOB_DIFF1 registers to power down if only 16 bits of DQ DDR are
used (including ECC bits).
9. For DDR2 and DDR3/DDR3L – DCI only affects termination strength, so address and clock
outputs do not use DCI.
10. For LPDDR2 – DCI affects drive strength, so all I/Os use DCI.
VREF Configuration
DDR I/Os use a differential input receiver. One input to this receiver is connected to the data input,
and the other is connected to a voltage reference called V
REF
. For DDR2/3 and LPDDR2 DRAM
interfaces, the V
REF
voltage is set to half of the I/O V
CCO
voltage. The V
REF
can be supplied either
externally over dedicated V
REF
pads, or from an internal voltage source. External V
REF
is
recommended for all designs to provide additional timing margin, but requires external board
components. To configure the V
REF
reference supply, set the DDRIOB_DDR_CTRL register as follows:
• To enable internal V
REF
°
Set DDRIOB_DDR_CTRL.VREF_EXT_EN to 00 (disconnect I/Os from external signal)
°
Set DDRIOB_DDR_CTRL.VREF_SEL to the appropriate voltage setting depending on the DDR
standard (V
REF
=V
CCO_DDR
/2)
°
Set DDRIOB_DDR_CTRL.VREF_INT_EN to 1 to enable the internal V
REF
generator
• To enable external V
REF
°
Set DDRIOB_DDR_CTRL.VREF_INT_EN to 0 to disable the internal V
REF
generator
°
Set DDRIOB_DDR_CTRL.VREF_SEL to 0000
°
Set DDRIOB_DDR_CTRL.VREF_EXT_EN to 11 to connect the IOBs V
REF
input to the external
pad for a 32-bit interface
°
Set DDRIOB_DDR_CTRL.VREF_EXT_EN to 01 to connect the IOBs V
REF
input to the external
pad for a 16-bit interface
10.6.4 DDR Controller Register Programming
Prior to enabling the DDRC, all DDRC registers must be initialized to system-specific values. About
80 registers with over 350 parameters might be set or left at their power-on default values. The DDRC
is then enabled, by writing to the ddrc_ctrl register. Once enabled, the DDRC automatically performs
the initialization steps 4-7 (Initialization and Calibration). DDRC operation is autonomous, requiring
no further programming unless functionality changes are desired (e.g. changing AXI port priority
levels).