User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 314
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
Training time is on the order of 1-2 ms at a 500 MHz DRAM clock.
Note: For training to be successful, all of the data signals need to be connected to the DRAM
device(s) even when ECC is used (16-bit data, 10-bit ECC).
Write Leveling
Goal Adjust WR DQS relative to CLK
Desired Nominal DQS aligned with clock (0 phase offset)
Final Ratio Equal to the DQS to CLK board delay at the DRAM
Initial Ratio Final value minus 0.5 cycle. If < 0 set to 0. If skew is too small, invert clock.
Applies To DDR3/DDR3L only
Write leveling is part of the DDR3/DDR3L specification. Due to the fly-by topology recommended for
DDR3/DDR3L systems, the clock (CLK) tends to lag relative to write DQS at the DRAM input. In order
to align CLK and DQS as required by the DRAM specification, the PHY delays the DQS signal to match
the board skew. The write leveling procedure is used to find the required delay.
When write leveling is enabled (via MR1), the DRAM asynchronously feeds back CLK, sampled with
the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition
from 0 to 1 is detected. Write leveling is performed independently for each byte lane. The calibration
logic OR's the DQ bits in a byte to determine the transition because different memory vendors use
different bits in a byte as feedback.
The DDRC supports write leveling as part of the initialization procedure. Optionally, write leveling
can be disabled and pre-determined delay values can be programmed via registers (required for
DDR2 and LPDDR2 where write leveling is not supported).
IMPORTANT: Successful training depends on providing an approximate minimum DQS to CLK delay
value. This value should be estimated based on system board layout as well as package delay
information.
Read DQS Gate Training
Goal Adjust valid RD DQS window.
Desired Nominal Surround the 4 (BL=8) valid DQS pulses
Final Ratio 2 * board delay. Add 0.5 cycle if the clock is inverted
Initial Ratio Final ratio minus 0.125 cycle (0x20 units), but not < 0.
Applies To DDR3/DDR3L, LPDDR2
The read DQS gate training is used by the PHY to identify the valid interval of read DQS and capture
the read data. It is necessary to align the valid read window to the read data burst and exclude the
preamble period and any period during which the DQS signal is tri-stated or driven by the PHY itself.