User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 315
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
The DDRC supports read DQS gate training as part of the initialization procedure. Optionally,
training can be disabled and pre-determined delay values can be programmed via registers (required
for DDR2, where read training is not supported).
Note that when using LPDDR2, with read gate training, automatic training is not recommended.
Instead, the following procedure is recommended (Xilinx tools implement this flow):
1. The even byte lanes are trained and the results are recorded by software.
2. The odd byte lanes are trained and the results are recorded by software.
3. The results from 1 and 2 are then applied during DRAM controller initialization, with automatic
training disabled.
IMPORTANT: Successful training depends on providing an approximate minimum Zynq-7000
AP SoC-to-DRAM board delay value. This value should be estimated based on system board layout.
Read Data Eye Training
Goal Adjust RD DQS relative to RD data.
Desired Nominal DQS edge in the middle of data eye
Final Ratio Nominal ideal value is 0.25 cycle since at DRAM output DQ and DQS are aligned
Initial Ratio None required
Applies To DDR3/DDR3L, LPDDR2
Enabled by the MPR bit-field in MR3, DDR3/DDR3L Read data eye training is done to compensate for
possible imbalanced loading on the read path. In this mode, the DRAM outputs a stream of
01010101 in a burst length of 8 bits with a regular memory read command. Given the known data
pattern, the memory controller adjusts the internal DQS delay so that DQS edges occur in the middle
of the data eye.
The DDRC supports read data eye training as part of the initialization procedure. Optionally, training
can be disabled and pre-determined delay values can be programmed via registers (required for
DDR2 where read training is not supported).
10.6.9 Write Data Eye Adjustment
There is no DDRC support for write data eye training, i.e., automatic alignment of write data relative
to write DQS (recall that write leveling adjusts write DQS relative to CLK). However, manual alignment
is possible.
Nominally, write DQS edges should be aligned in the middle of the write data eye at the DRAM
inputs. The DDRC PHY provides a user-programmable phase shift value of data relative to DQS. The
default nominal value is a 90 degrees phase shift. Given a balanced board design in which the DQ
and DQS signals exhibit the same delay and loading, the default value is adequate. Otherwise, the
user can provide a different phase shift value. The recommended value based on characterization