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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 317
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
As final parameters, pick the values that are in the center of the successful tests region. Note that
each data byte lane (aka data slice) has its own independent parameters, and should be tested
independently in the memory tests.
The estimated time for a training iteration is 1-2 ms plus the duration of the memory test. Assuming
a simple 1,000 word read-write test and an average access time of 30 cycles, test duration is on the
order of 60,000 cycles or about 0.12 ms at 500 MHz. Thus, a 25-iteration semi-automatic training
might last 25-50 ms.
Multi-Set Semi-Automatic Training
RECOMMENDED: Before resorting to manual training, a multi-set semi automatic training method is
recommended.
The DDR PHY contains five adjustable delay elements, four of which are per byte lane (so the actual
number of unique adjustable delay elements is 17). Of these five elements, only three are adjusted by
the automatic training. These three elements are the write DQS delay, read DQS delay, and read data
delay. The remaining two elements are the write data delay, and the control path delay, which take
their value from a programmable register, and the value is not adjusted by the automatic training.
The automatic training process varies the delay of those three elements over a wide range, and the
semi-automatic procedure increases that range. If both automatic and semi-automatic procedures
fail, it is highly likely that one or both of the remaining two delay elements require adjustment.
Therefore, multiple sets of semi-automatic training procedures can be run, each set using different
values of the two remaining delay values. Thus we still take advantage of the efficiency of the
automatic training, and reduce the total number of experiments compared to all-manual training.
Manual Training
This method is useful when nothing is known, or if the semi-automatic method has failed. In its
simplest form, this method consists of:
• Disabling the automatic training
• Performing a manual sweep of all delay parameters over their entire range. For each setting:
°
Initialize the DDRC with training disabled
°
Perform a memory test
• Keeping a scoreboard of results
• Locating the mid-point of all delay parameters (which might be different for each data lane)
The recommended delay increment value per iteration is 1/32 of a clock cycle, thus requiring 32
iterations to cover a one-cycle delay range per parameter.
The estimated time for a manual training iteration is 700 us (500 us are required as part of the DRAM
reset/initialization procedure for DDR3/DDR3L) plus the duration of the memory test, or about
0.8 ms. Simplifying assumptions can be used to reduce the search range, but even then the number
of iterations might be on the order of 1,000, bringing the manual training time to about one second.