User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 323
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
• Sends the corrected data to the core as part of the read data.
• Sends the ECC error information to the register interface for logging.
• Performs a RMW operation to correct the data present in the DRAM (only if ECC scrubbing is
enabled (reg_ddrc_dis_scrub = 0). This RMW operation is invisible to the core. Only one scrub
RMW command can be outstanding in the controller at any time. No scrub is performed on
single-bit ECC errors that occur while the controller is processing another scrub RMW.
When the controller detects an uncorrectable error, it does the following:
• Sends the uncorrectable data with an error response to the core. This results in an AXI SLVERR
response on the AXI interface along with the corrupted data. An AXI SLVERR response will be
returned to the transaction master to be handled – potentially generating L2/DMA interrupts,
CPU prefetch/data exceptions, or being forwarded directly to a PL AXI master.
• Sends the ECC error information to the register module for logging.
10.8.3 Data Mask During ECC Mode
ECC is calculated over a byte of data and hence any data byte can be masked if necessary with ECC
enabled. This alleviates the need for the controller to perform a RMW operation when byte masking
occurs.
10.8.4 ECC Programming Model
The following details the ECC programming requirements. Note that these configurations are in
addition to the regular DDR initialization programming. Also note that initialization of the whole
DDR space before reading any data from it is recommended, to prevent ECC error generation as a
result of accessing uninitialized areas of memory. Refer to section 10.8.1 ECC Initialization section
for further details.
Enabling ECC operation (Switching from Non-ECC Mode to ECC Mode)
1. Program reg_ddrc_soft_rstb to 0 (resets the controller)
2. Program the ECC mode by programming reg_ddrc_ecc_mode to 3'b100
3. Program reg_ddrc_dis_scrub to 1'b0
4. Program reg_ddrc_data_bus_width to 2'b0
5. Program reg_ddrc_soft_rstb to 1 (takes the controller out of reset)
Note that re-initialization of the whole DDR space before reading any data from it is recommended
to prevent ECC error generation as a result of accessing uninitialized areas of memory.
Disabling the ECC Operation (Switching from ECC Mode to Non-ECC Mode)
1. Program the reg_ddrc_soft_rstb to 0 (resets the controller)
2. Program the ECC mode by programming the reg_ddrc_ecc_mode to 3'b000
3. Program the reg_ddrc_dis_scrub to 1'b1
4. Program the reg_ddrc_data_bus_width to 2'b00