User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 324
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
5. Program the reg_ddrc_soft_rstb to 1 (takes the controller out of reset)
Monitoring ECC Status
1. CHE_CORR_ECC_ADDR_REG_OFFSET gives the bank/row/column information of the ECC error
correction
2. CHE_UNCORR_ECC_ADDR_REG_OFFSET gives the bank/row/column information of the ECC
unrecoverable error
3. B[0] of CHE_CORR_ECC_LOG_REG_OFFSET indicates correctable ECC status
4. B[0] of CHE_UNCORR_ECC_LOG_REG_OFFSET indicates uncorrectable ECC status
5. CHE_ECC_STATS_REG_OFFSET
°
B[7:0] -> gives the number of uncorrectable errors
°
B[15:8] -> gives the number of correctable errors
10.9 Programming Model
10.9.1 Operating Modes
The operating mode register bits, mode_sts_reg.ddrc_reg_operating_mode, can be polled to
determine the current mode of operation of the controller. The different modes are:
• 000 – uninitialized. The controller might be in soft reset, or it might be out of soft reset, but
DRAM initialization sequence has not yet completed.
• 001 – normal operating mode. The controller is ready to accept read and write requests and the
controller can issue reads and writes to DRAM.
• 010 – DRAM is in power down mode.
• 011 – DRAM is in self refresh mode.
• 100 : 111 – For LPDDR2 designs only, indicates DRAM is in deep power down.
10.9.2 Changing Clock Frequencies
The process of changing clock frequencies is as follows:
1. Request the controller to place the DRAM into self refresh mode, by asserting
ctrl_reg1.reg_ddrc_selfref_en.
2. Wait until mode_sts_reg.ddrc_reg_operating_mode[1:0]== 11 indicating that the controller is in
self refresh mode. In the case of LPDDR2 check that ddrc_reg_operating_mode[2:0]== 011.
3. Change the clock frequency to the controller (see 10.6.1 DDR Clock Initialization).
4. Update any registers which might be required to change for the new frequency. This includes
static and dynamic registers. If the updated registers involve any of reg_ddrc_mr, reg_ddrc_emr,
reg_ddrc_emr2 or reg_ddrc_emr3, then go to step 5. Otherwise go to step 6.