User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 326
UG585 (v1.11) September 27, 2016
Chapter 10: DDR Memory Controller
10.9.6 DDR Power Reduction
Clock Stop
When this feature is enabled, the DDR PHY is allowed to stop the clocks going to the DRAM. For
DDR2 and DDR3/DDR3L this feature is effective in self refresh mode only. For LPDDR2 this feature
becomes effective in:
•Idle periods
• Power down mode
• Self refresh mode
• Deep power down mode
Precharge Power Down
When enabled, the DDR memory controller dynamically uses precharge power down mode to reduce
power consumption during idle periods. Normal operation continues when a new request is received
by the DDRC.
Self Refresh
When enabled the DDRC dynamically puts the DRAM into self-refresh mode during idle periods.
Normal operation continues when a new request is received by the DDRC. In this mode DRAM
contents are maintained even when the DDRC core logic is fully powered down, thus allowing to stop
the DDR2X and DDR3X/DDR3LX clocks. Also the DCI clock, which controls the DDR termination, can
be shut down.
Self Refresh Sequence
To put the DDR memory into self-refresh mode the following sequence can be used. When executing
these steps, the executing CPU should be the only still active master, to guarantee that no new
requests are issued to the DDR memory. This mode is typically used in sleep mode. Note that in the
following sequence, T
ddr
is the period of the DDR clock.
ddrc.ctrl_reg1[reg_ddrc_selfref_en] = 1
ddrc.DRAM_param_reg3 [reg_ddrc_en_dfi_dram_clk_disable] = 1
while (ddrc.mode_sts_reg[ddrc_reg_operating_mode] != 3)
while (ddrc.mode_sts_reg[ddrc_reg_dbg_hpr_q_depth] ||
ddrc.mode_sts_reg[ddrc_reg_dbg_lpr_q_depth] ||
ddrc.mode_sts_reg[ddrc_reg_dbg_wr_q_depth)
delay(40 * T
ddr
)
slcr.DDR_CLK_CTRL[DDR_2XCLKACT] = 0
slcr.DDR_CLK_CTRL[DDR_3XCLKACT] = 0
slcr.DCI_CLK_CTRL[CLKACT] = 0
To resume normal DDR operation the clocks must be re-enabled first. Then DRAM is accessible again
and the clock stop and self-refresh features can be disabled.
IMPORTANT: Precharge power down and self refresh modes are mutually exclusive and must not be
activated at the same time.