User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 333
UG585 (v1.11) September 27, 2016
Chapter 11: Static Memory Controller
Optional Pins
• For either SRAM or NOR, the upper address bits are optional. When not used, they can be
assigned to other functions.
Table 11-5: SMC MIO Pins
MIO
Pin
SRAM/NOR Interface Mode
MIO
Pin
NAND Flash Interface Mode
Signal Name I/O
Default
Value
Description Signal Name I/O
Default
Value
Description
MIO Voltage Bank 0
0 SRAM_CE_B[0] O - SRAM/NOR chip sel 0 0 NAND_CE_B O - NAND chip select
1 SRAM_CE_B[1] O - SRAM/NOR chip sel 1 1 - - - -
2 - - - - 2 NAND_ALE O - NAND address latch
3 SRAM_DQ[0] IO 0 SRAM/NOR data 3 NAND_WE_B O - NAND write enable
4 SRAM_DQ[1] IO 0 SRAM/NOR data 4 NAND_IO[2] IO 0
NAND
data/address/cmd
5 SRAM_DQ[2] IO 0 SRAM/NOR data 5 NAND_IO[0] IO 0
NAND
data/address/cmd
6 SRAM_DQ[3] IO 0 SRAM/NOR data 6 NAND_IO[1] IO 0
NAND
data/address/cmd
7 SRAM_OE_B O - SRAM/NOR output en 7 NAND_CLE O - NAND chip select
8 SRAM_BLS_B O - SRAM/NOR write en 8 NAND_RE_B O - NAND read enable
9 SRAM_DQ[6] IO 0 SRAM/NOR data 9 NAND_IO[4] IO 0
NAND
data/address/cmd
10 SRAM_DQ[7] IO 0 SRAM/NOR data 10 NAND_IO[5] IO 0
NAND
data/address/cmd
11 SRAM_DQ[4] IO 0 SRAM/NOR data 11 NAND_IO[6] IO 0
NAND
data/address/cmd
12 - - - - 12 NAND_IO[7] IO 0
NAND
data/address/cmd
13 SRAM_DQ[5] IO 0 SRAM/NOR data 13 NAND_IO[3] IO 0
NAND
data/address/cmd
14 - - - - 14 NAND_BUSY I 0 NAND busy
15 SRAM_A[0] O - SRAM/NOR address 15 - - - -
MIO Voltage Bank 1
23:16 SRAM_A [8:1] O - SRAM/NOR address 23:16 NAND_IO [15:8] IO 0
NAND
data/address/cmd
39:24 SRAM_A [24:9] O - SRAM/NOR address 39:24 - - - -