User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 341
UG585 (v1.11) September 27, 2016
Chapter 12: Quad-SPI Flash Controller
content of the TxFIFO, it concurrently samples the raw serial data, performs serial-to-parallel
conversion, and stores data into RxFIFO.
In the case of a read command, when data is to be driven by the flash memory after the command
and address bytes, the MIO switches from output to input at the appropriate time under the control
of the transmit logic. Data shifted into the RxFIFO reflects the switch resulting in valid data in the
RxFIFO at the corresponding FIFO entry
Software needs to filter the raw data from the RxFIFO to obtain the relevant data content. The
controller does not modify either the instruction written by software or the captured data put into
the RxFIFO.
The controller supports little endian mode and the most significant bit of the least significant byte
of a 4-byte word of an instruction is sent first.
Flow Control
I/O mode has different modes of flow control during data transfer. The user can select between
automatic and manual mode, controlled by config_reg.MANSTARTEN (Man_start_com). In Manual
mode, the user can further select manual or automatic chip select with Config_reg.SSFORCE
(Manaual_CS). Asserting chip select signals the beginning of a command sequence on MIO.
Immediately following the CS assertion, serial data on D0 is interpreted as command by the flash
memory.
In automatic mode, the entire transmission sequence, including control of chip select is done in
hardware. No software intervention is required. The transmission starts as soon as data is pushed
into the TxFIFO via writing to TXD, chip select automatically becomes active. Data transmission ends
when the TxFIFO is empty and chip select automatically becomes inactive. In this mode, to carry out
continuous data transfer, software must be able to keep up with supplying data to the TxFIFO at a
rate equal or higher than the rate of data movement on the MIO. This can be difficult since reading
from RXD and writing to TXD occurs at the APB clock rate.
In Manual mode, the user controls the start of data transmission. In this case, software either writes
the entire transmission sequence to the TxFIFO or until the TxFIFO is full. Upon writing of the
Man_start_en bit, the controller takes over, asserts CS, shifts data out of the TxFIFO and into the
RxFIFO, controls the input/ouput state of the MIO as appropriate, and terminates the sequence when
the TxFIFO is empty by de-asserting CS. The maximum number of bytes per command sequence in
this mode is limited by the depth of the TxFIFO of 252 bytes.
In manual mode, the user can further choose to control the chip select in addition to controlling the
start of transmission. Software again writes the transmission sequence to the TxFIFO starting with
the command until the TxFIFO is full. Software then asserts CS, followed by manual start. The
hardware takes over. However, CS is not de-asserted when the TxFIFO becomes empty. Software can
fill the TxFIFO again with the appropriate data to continue the previous command. This method
removes the limit on the number of bytes per command sequence and can be used effectively for
large data transfers. On completion of the command sequence, the software de-asserts CS by writing
to the Manual_CS bit.