User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 346
UG585 (v1.11) September 27, 2016
Chapter 12: Quad-SPI Flash Controller
12.2.6 Unsupported Devices
A number of devices implement custom 4-bit wide SPI-like interfaces for flash memory access, such
as the SQI devices from SST, and the Fast4 devices from Atmel. Some other Quad-SPI devices, like
some Micron/Numonyx devices, offer an option to switch operation to such a custom 4-bit interface,
through a non-volatile configuration bit.
These interfaces operate differently from the devices supported by the Quad-SPI controller. These
flash memory devices operate in 4-bit mode during the instruction phase, as well as the address and
data phases. This requires the Quad-SPI flash controller to power up in 4-bit mode and remain in that
mode permanently (or until configured otherwise, if that option is available). There are no plans to
enable the support for these custom interfaces.
12.2.7 Supported Memory Read and Write Commands
Supports commands that transfers address one bit per rising edge of SCK and return data 1, 2, or 4
bits of data per rising edge of SCK. These commands are called Read or Fast Read for 1-bit data; Dual
Output Read for 2-bit data, and Quad Output for 4-bit data.
Supports commands that transfer both address and data 2 or 4 bits per rising edge of SCK. These are
called Dual I/O for 2-bit and Quad I/O for 4-bit.
Table 12-4: Memory Read and Write Commands
Instruction
Name
Description Code(Hex)
READ Read. Single-bit address sent for every rising edge of clock.
Data returned one bit per rising edge of SCLK.
03
FAST_READ Read Fast. Single-bit address sent for every rising edge of
clock. Data returned one bit per rising edge of SCLK.
0B
DOR Read Dual Out. Single-bit address sent for every rising edge of
clock. Data returned two bits per rising edge of SCLK.
3B
QOR Read Quad Out. Single-bit address sent for every rising edge
of clock. Data returned four bits per rising edge of SCLK.
6B
DIOR Dual I/O Read. Two-bit address sent for every rising edge of
clock. Data returned four bits per rising edge of SCLK.
BB
QIOR Quad I/O Read. Four-bit address sent for every rising edge of
clock. Data returned four bits per rising edge of SCLK.
EB
PP Page Program. Single-bit address sent for every rising edge of
clock. Data sent single bit per rising edge of SCLK.
02
QPP Quad Page Program. Single-bit address sent for every rising
edge of clock. Data sent four bits per rising edge of SCLK.
32 in case of Spansion and
Micron devices.
38 in case of Macronix
devices.