User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 348
UG585 (v1.11) September 27, 2016
Chapter 12: Quad-SPI Flash Controller
12.3.2 Linear Addressing Mode
Example: Linear Addressing Mode (Memory Reads)
The sequence of operations for data reads in linear addressing mode is as follows:
1. Set manual start enable to auto mode. Set qspi.Config_reg[Man_start_en] = 0.
2. Assert the chip select. Set qspi.Config_reg[PCS] = 0.
3. Program the configuration register for linear addressing mode. Example values are shown in
Table 12-3, page 344.
4. Enable the controller. Set qspi.En_REG[SPI_EN] = 1.
5. Read data from the linear address memory region. The memory range depends on the size
and number of devices. The range is from 0xFC00_0000 up to 0xFDFF_FFFF.
6. Disable the controller. Set qspi.En_REG[SPI_EN] = 0.
7. De-assert chip select. Set qspi.Config_reg[PCS] = 1.
12.3.3 Configure I/O Mode
Example: I/O Mode (Memory Reads and Writes)
The sequence of operations uses I/O mode for reads and writes.
1. Enable manual mode. Write 1 to qspi.Config_reg[Man_start_en, Manual_CS] = 1.
2. Configure the flash device. Refer to Figure 12-6, page 355. Use reset values of the
qspi.LQSPI_CFG register for a single flash device. In case of a parallel dual flash device, write 1 to
the TWO_MEM, SEP_BUS bit fields.
3. Assert chip select. Set qspi.Config_reg[PCS] = 0.
4. Enable the controller. Set qspi.En_REG[SPI_EN] = 1.
5. Write byte sequences to the flash memory. Write from 1 to 4 bytes to the TxFIFO using the TXD
registers. Refer to section 12.2.3 I/O Mode Transmit Registers (TXD).
6. Avoid TxFIFO overflow. When the TxFIFO is empty, 252 bytes can be written. After that, software
can avoid overflowing the TxFIFO by reading qspi.Intr_status_REG[TX_FIFO_full] and waiting until
it equals 0 before writing to a TXD register.
7. Enable the interrupts. Write to qspi.Intrpt_en_REG. Interrupt handlers that handle the interrupt
conditions are discussed in interrupt handlers section.
8. Start data transfer. Set qspi.Config_reg[Man_start_com] = 1.
9. Interrupt handler: Transfer all the required data to QSPI flash during program/read operations
to Quad-SPI flash. (See Example: I/O Mode Interrupt Service Routine, page 349.)
10. If read operations are carried out: re-arrange the READ data to eliminate the data read due to
dummy cycles.
11. Disable controller. Set qspi.En_REG[SPI_EN] = 0.
12. De-assert chip select. Set QSPI.Config_reg[PCS] = 1.