User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 349
UG585 (v1.11) September 27, 2016
Chapter 12: Quad-SPI Flash Controller
Note that the TxFIFO width must be programmed to 32 bits: qspi.Config_reg[FIFO_WIDTH] = 0b11.
Software needs to take care of “consecutive non word aligned” transfers.
Example: I/O Mode Interrupt Service Routine
1. Configure the ISR to handle the interrupt conditions based on the Quad-SPI device type. To
read from the Quad-SPI device, the simplest ISR reads data from the RxFIFO and writes content
to the TxFIFO. The system interrupt controller (GIC) is described in Chapter 7, Interrupts. The
controller generates a system peripheral interrupt (SPI), IRQ ID #51. The interrupt mechanism for
the Quad-SPI controller is described in section 12.3.4 I/O Mode Interrupts.
a. Read transfer interrupt. RxFIFO Not Empty Interrupt
b. Write transfer interrupt. TxFIFO Not Full Interrupt
12.3.4 I/O Mode Interrupts
Interrupts are only used in I/O mode. The controller interrupt is asserted whenever any of the
interrupt conditions are met. The Quad-SPI interrupt handler checks the cause of the interrupt. A
single interrupt service routine can manage all of the interrupt conditions.
Example: Interrupt Handler for Rx and Tx
The interrupt handler is trigger by IRQ ID #51. The example reads the RxFIFO until it is empty and
then fills-up the TxFIFO. The RxFIFO Not Empty Interrupt status is used to determine if content can
be read from the RxFIFO. The TxFIFO Not Full interrupt indicates if there is room in the TxFIFO for
more content.
1. Disable all of the interrupts in the controller. Set qspi.Intrpt_dis_REG[TX_FIFO_not_full,
RX_FIFO_full] both = 1.
2. Clear the interrupts. Read the interrupt status register qspi.Intr_status_REG.
3. Empty the RxFIFO. Check if RxFIFO Not Empty interrupt is asserted. If
qspi.Intr_status_REG[RX_FIFO_not_empty] = 1, then there is data in the RxFIFO.
a. If the status is asserted, then read data from the RxFIFO. Read the data using the
qspi.RX_data_REG register.
b. Read data from the RxFIFO and poll the interrupt status until the RxFIFO is empty. The
RxFIFO is empty when qspi.Intr_status_REG[RX_FIFO_not_empty] = 0.
4. Fill the TxFIFO. Check if the TxFIFO Not Full status is asserted. If
qspi.Intr_status_REG[TX_FIFO_not_Full] = 1, then there is data to be sent to the flash device
(program and/or read operations):
a. Write data to the qspi.TXD0 register.
b. Poll for qspi.Intr_status_REG[TX_FIFO_full] = 1, which indicates TX FIFO is full.
c. Follow steps a and b until all the data is written to the TxFIFO or until
qspi.Intr_status_REG[TX_FIFO_full] = 1.
5. Enable the interrupts. Set qspi.Intrpt_en_REG[TX_FIFO_not_full, RX_FIFO_full] both = 1.
6. Start the data transfer. Set qspi.Config_reg[MANSTRTEN] = 1.