User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 353
UG585 (v1.11) September 27, 2016
Chapter 12: Quad-SPI Flash Controller
CPU_1x Clock
Refer to section 25.2 CPU Clock, for general clock programming information. The CPU_1x clock runs
asynchronous to the Quad-SPI reference clock.
QSPI_REF_CLK and Quad-SPI Interface Clocks
The QSPI_REF_CLK is the main controller clock. The QSPI_REF_CLK is sourced from the PS Clock
Subsystem. The clock enable, PLL select, and divisor setting are programmed using the
slcr.LQSPI_CLK_CTRL register. Refer to section 25.6.3 SDIO, SMC, SPI, Quad-SPI and UART Clocks to
program the QSPI_REF_CLK frequency.
To generate the Quad-SPI interface clock, the QSPI_REF_CLK is divided down by 2, 4, 8, 16, 32, 64,
128, or 256 using the qspi.Config_reg [BAUD_RATE_DIV] bit field.
For power management, the clock enable in the slcr register can be used to turn off the clock. The
operating frequency for the reference clock is defined in the data sheet.
Clock Ratio Restriction in Manual Mode
In manual mode, the QSPI_REF_CLK frequency must be of greater than or equal value to that of
CPU_1x clock frequency for reliable operation of the controller.
There is no such restriction in automatic mode.The reference clock is divided down by
qspi.Config_reg[baud_rate_divisor] to generate the SCLK clock for the flash memory.
Example: Setup Reference Clock
This example assumes the selected PLL (ARM, DDR or IO) is operating at 1000 MHz and the desired
Quad-SPI reference clock frequency is 200 MHz.
1. Select PLL source, divisors and enable. Write 0x0000_0501 to the slcr.QSPI_CLK_CTRL
register.
a. Enable the reference clock.
b. Divide the I/O PLL clock by 5: DIVISOR = 0x05.
c. Select the I/O PLL as the clock source.
Quad-SPI Feedback Clock
The Quad-SPI interface supports an optional feedback clock pin named qspi_sclk_fb_out. This pin is
used with the high speed Quad-SPI timing mode, where the memory interface clock needs to be
greater than 40 MHz. The feedback signal is received from the internal input from the I/O so MIO pin
8 needs to be programmed and allowed to freely toggle. Refer to optional programming example in
section 12.5.2 MIO Programming for instructions on how to program the MIO_PIN_08 register.
When Quad-SPI feedback mode is used, the qspi_sclk_fb_out pin should only be connected to a
pull-up or pull-down resistor which is needed to set the MIO voltage mode (vmode).