User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 369
UG585 (v1.11) September 27, 2016
Chapter 13: SD/SDIO Controller
The sequence for data transfers without using DMA is as follows:
1. Set the value corresponding to the executed data byte length of one block to the Block Size
register.
2. Set the value corresponding to the executed data block count to the Block Count register.
3. Set the value corresponding to the issued command to the Argument register.
4. Set the value to Multi/Single Block Select and Block Count Enable. Set the value corresponding
to the issued command to Data Transfer Direction, Auto CMD12 Enable, and DMA Enable.
5. Set the value corresponding to the issued command to the Command register.
Note: When writing the upper byte of the command register, the SD command is issued.
6. Wait for the command complete interrupt.
7. Write a 1 to the Command Complete bit in the Normal Interrupt Status register to clear this bit.
8. Read the Response register and get the necessary information in accordance with the issued
command.
9. In the case where this sequence is for writing to a card, go to Step (10-W). In case of read from
a card, go to Step (10-R).
(10-W). Wait for a buffer write ready interrupt.
°
Non-DMA Write Transfer
On receiving the buffer write ready interrupt the ARM processor acts as a master and starts
transferring the data via the Buffer Data Port register (FIFO_1). The transmitter starts sending
the data on the SD bus when a block of data is ready in FIFO_1. While transmitting the data
on the SD bus the buffer write ready interrupt is sent to the ARM processor for the second
block of data. The ARM processor acts as a master and starts sending the second block of
data via the buffer data port register to FIFO_2. The buffer write ready interrupt is asserted
only when a FIFO is empty and available to receive a block of data.
(11-W). Write a 1 to the Buffer Write Ready bit in the Normal Interrupt Status register to clear this
bit.
(12-W). Write a block of data (according to the number of bytes specified in Step (1)) to the Buffer
Data Port register.
(13-W). Repeat until all blocks are sent and then go to Step (14).
°
Non-DMA Read Transfer
A buffer read ready interrupt is asserted whenever a block of data is ready in one of the
FIFOs. On receiving the buffer read ready interrupt, the ARM processor acts as a master and
starts reading the data via the Buffer Data Port register (FIFO_1). The receiver starts reading
the data from the SD bus only when a FIFO is empty and available to receive a block of data.
When both of the FIFOs are full the host controller stops the data coming from the card by
means of a read wait mechanism (if the card supports read wait) or through clock stopping.
(10-R). Wait for a buffer read ready interrupt
(11-R). Write a 1 to the Buffer Read Ready bit in the Normal Interrupt Status register to clear this bit.