User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 374
UG585 (v1.11) September 27, 2016
Chapter 13: SD/SDIO Controller
If the Block Count Enable bit in the Transfer Mode register is set to 1, the total data length can
be designated by the Block Count register and the descriptor table. These two parameters shall
indicate same data length. However, transfer length is limited by the 16-bit Block Count register.
If the Block Count Enable bit in the Transfer Mode register is set to 0, the total data length is
designated not by Block Count register, but the descriptor table. In this case, if the ADMA reads
more data than the length programmed in the descriptor from the SD card, the operation is
aborted asynchronously and the extra read data is discarded when the ADMA is completed.
5. Set the argument value to the Argument register.
6. Set the value to the Transfer Mode register. The host driver determines Multi/Single Block Select,
Block Count Enable, Data Transfer Direction, Auto CMD12 Enable and DMA Enable. Multi/Single
Block Select and Block Count Enable are determined according to SDIO register map.
7. Set the value to the Command register.
Note: When writing to the upper byte [3] of the Command register, the SD command is issued
and DMA is started.
8. Wait for the command complete interrupt.
9. Write a 1 to the Command Complete bit in the Normal Interrupt Status register to clear this bit.
10. Read the Response register and get the necessary information from the issued command.
11. Wait for the transfer complete interrupt and ADMA error interrupt.
12. If the Transfer Complete is set to 1, go to Step (13). If the ADMA Error Interrupt is set to 1, go to
Step (14).
13. Write a 1 to the Transfer Complete Status bit in the Normal Interrupt Status register to clear this
bit.
14. Write a 1 to the ADMA Error Interrupt Status bit in the Error Interrupt Status register to clear this
bit.
15. Abort ADMA operation. SD card operation should be stopped by issuing an abort command. If
necessary, the host driver checks the ADMA Error Status register to detect why the ADMA error
is generated.
Note: Step (3) and Step (4) can be executed simultaneously. Step (6) and Step (7) can also be
executed simultaneously.
Note: During ADMA2 operation, the controller will not generate a DMA interrupt if the INT attribute
is set along with NOP, RSVD, or LINK attribute.
13.3.5 Abort Transaction
An abort transaction is performed using CMD12 for a SD memory card and by using CMD52 for a
SDIO card. There are two cases where the HD needs to do an abort transaction:
• When the HD stops infinite block transfers.
• When the HD stops transfers while a multiple block transfer is executing.
There are two ways to issue an abort command. The first is an asynchronous abort. The second is a
synchronous abort. In an asynchronous abort sequence, the HD can issue an abort command at
anytime unless the Command Inhibit (CMD) bit in the Present State register is set to 1. In a
synchronous abort, the HD issues an abort command after the data transfer stopped via the Stop At
Block Gap Request bit in the Block Gap Control register.