User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 384
UG585 (v1.11) September 27, 2016
Chapter 14: General Purpose I/O (GPIO)
• DATA: This register controls the value to be output when the GPIO signal is configured as an
output. All 32 bits of this register are written at one time. Reading from this register returns the
previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the current
value on the device pin.
• MASK_DATA_LSW: This register enables more selective changes to the desired output value.
Any combination of up to 16 bits can be written. Those bits that are not written are unchanged
and hold their previous value. Reading from this register returns the previous value written to
either DATA or MASK_DATA_{LSW,MSW}; it does not return the current value on the device pin.
This register avoids the need for a read-modify-write sequence for unchanged bits.
• MASK_DATA_MSW: This register is the same as MASK_DATA_LSW, except it controls the
upper16 bits of the bank.
• DIRM: Direction Mode. This controls whether the I/O pin is acting as an input or an output.
Since the input logic is always enabled, this effectively enables/disables the output driver. When
DIRM[x]==0, the output driver is disabled.
• OEN: Output Enable. When the I/O is configured as an output, this controls whether the output
is enabled or not. When the output is disabled, the pin is 3-stated. When OEN[x]==0, the output
driver is disabled.
Note: If MIO TRI_ENABLE is set to 1, enabling 3-state and disabling the driver, then OEN is
ignored and the output is 3-stated.
14.2.2 EMIO Signals
This section describes the operation of Bank2 and Bank3 (see Figure 14-2).
The register interface for the EMIO banks is the same as for the MIO banks described in the previous
section. However, the EMIO interface is simply wires between the PS and the PL, so there are a few
differences:
• The inputs are wires from the PL and are unrelated to the output values or the OEN register.
They can be read from the DATA_RO register when DIRM is set to 0, making it an input.
• The output wires are not 3-state capable, so they are unaffected by OEN. The value to be output
is programmed using the DATA, MASK_DATA_LSW, and MASK_DATA_MSW registers. DIRM must
be set to 1, making it an output.
• The output enable wires are simply outputs from the PS. These are controlled by the DIRM/OEN
registers as follows: EMIOGPIOTN[x] = DIRM[x] & OEN[x]
The EMIO I/Os are not connected to the MIO I/Os in any way. The EMIO inputs cannot be connected
to the MIO outputs and the MIO inputs cannot be connected to the EMIO outputs. Each bank is
independent and can only be used as software observable/controllable signals.
14.2.3 Bank0, Bits[8:7] are Outputs
GPIO bits[8:7] of Bank0 correspond to package pins that are used to control the voltage mode of the
I/O buffers themselves during reset. These pins are called the VMODE pin straps for the MIO banks
(see section Boot Mode Pin Settings, page 165). They must be driven by the external system
according to the proper voltage mode. To prevent them from being driven by other system logic,
they cannot be used as general purpose inputs.