User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 390
UG585 (v1.11) September 27, 2016
Chapter 15
USB Host, Device, and OTG Controller
15.1 Introduction
The USB controller is capable of fulfilling a wide range of applications for USB 2.0 implementations
as a host, a device, or On-the-Go. Two identical controllers are in the Zynq-7000 device. Each
controller is configured and controlled independently. The USB controller I/O uses the ULPI protocol
to connect external ULPI PHY via the MIO pins. The ULPI interface provides an 8-bit parallel SDR data
path from the controller’s internal UTMI-like bus to the PHY. The ULPI interface minimizes device pin
count and is controlled by a 60 MHz clock output from the PHY.
USB is a cable bus that supports data exchange between a host device and a wide range of computer
peripherals. The attached peripherals share USB bandwidth through a host-scheduled, token-based
protocol. The bus allows peripherals to be attached, configured, used, and detached while the host
and other peripherals remain operational.
The USB controller in USB 2.0 Host compatible with the EHCI specification with some enhancements
and minor deviations. The OTG operating mode software switches the controller between Idle and
either Device or Host mode as needed by the application using the Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP).
The controller is designed to make efficient use of the system resources in an SoC design. The DMA
engine is responsible for moving USB transaction data between the Rx/Tx FIFOs and system memory.
The FIFOs are used to buffer the high-speed USB data rates with periodic delays associated with the
PS Interconnect data transfers.
The EHCI-compatible host controller is a schedule driven environment for data transfers of periodic
(interrupt and isochronous) and asynchronous (control and bulk) types. Device mode includes a
simple pair of descriptors to respond to USB data transfers in a timely manner between the software
and USB.
The transfer descriptors of the host schedules and device endpoints control the DMA engine to move
data between the 32-bit AHB master system bus interface and the Rx and Tx data FIFOs that respond
in real-time to the USB.
The controller makes strategic use of software for tasks that do not require time-critical responses.
This approach reduces the amount of hardware logic. At the same time, the controller includes
hardware assistance logic to enable the controller to respond quickly to USB events and simplify the
software.