User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 394
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
• Port Indicator and Power Pins via EMIO. The USB port indicator outputs, power select output,
and power fault input signals are routed through the EMIO to the SelectIO pins in the PL and
external board logic.
15.1.4 Controller Block Diagram
The controller interfaces to the PS system memory on one side and an external ULPI PHY device on
the USB side. A block diagram is shown in Figure 15-3. A detailed functional block is shown in section
15.1.9 Notices.
System Memory
The PS system memory is accessible to the DMA engine that holds transfer descriptors and data
buffers. The system memory can be DDR, OCM and memory that is mapped in the PL. The system
memory map is shown in section 4.1 Address Map. In this table, the USB controller is one of the
“Other Bus Masters,” refer to the table footnotes.
DMA, Protocol Engines, Context and FIFOs
The DMA engine works with the Protocol engine to process endpoints, periodic elements, queue
heads, and other transfer descriptors. Software writes these data structures into the system memory.
The DMA engine fetches these data structures and copies them into the controller’s local
dual-ported RAM (DPRAM). The controller reads and writes the data structures in the DPRAM as the
data structures are processed. The descriptors are written back to memory by the DMA engine when
a transfer is complete.
In addition to the context information of the data structures, the dual-port RAM is also used by the
controller to implement Rx and Tx data FIFOs. These FIFOs decouple the system processor memory
bus transfers from the real-time requirements of the USB.
The use of the FIFOs differs between host and device mode operation. In Host mode, a single data
channel is maintained in each direction through the dual-port RAM. In Device mode, multiple FIFO
channels are maintained for each of the active device endpoints and their direction(s).
X-Ref Target - Figure 15-3
Figure 15-3: USB Controller Block Diagram
UG585_c15_32_030713
DMA
Engine
System
Memory
ULPI
Link
Wrapper
USB Controller (Host and Device)
AHB
Similar to
UTMI+
Protocol
Engine
Port
Controller
Interface
MIO
Zynq-7000 AP SoC
ULPI
PHY
Dual-port
RAM
Rx & Tx
FIFOs
Dual-port
RAM
Context