User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 397
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Device Mode
As requested by the host, the Device Controller Driver (DCD) sets up descriptors for endpoints and
manages the real-time needs of the endpoints. The high-speed data transfers between memory and
ULPI are managed by the controller using queue heads and transfer descriptors. The results of each
transfer is reviewed by DCD to take appropriate action.
Device Endpoints. The device controller includes a simple descriptor model to enable the controller
to quickly respond to host requests. Each of the 12 endpoints has two device Queue Heads (dQH);
one for IN and the other for OUT transfer types. There are a total of 24 device dQH’s. An endpoint
data transfer in defined with one dQH and one or more linked list of device Transfer Descriptors
(dTD). An example is shown in Figure 15-13.
Host Mode
Host Schedules. The Host Controller Driver (HCD) maintains two types of transaction schedules to
generate USB traffic: periodic (isochronous/interrupt) and asynchronous (bulk/control).
• The Periodic schedule is a list of high to low priority-order periodic transfers. An element in the
periodic frame list is executed at the start of every frame (SOF). The list includes elements that
indicate when to execute (periodic interval) and what to execute. An example is shown in
Figure 15-15.
• The asynchronous schedule is a circular loop of Queue Heads that point to transfer descriptors
that are processed in a round-robin priority. Within each microframe, the asynchronous
schedule is executed after the periodic schedule is finished. An example is shown in
Figure 15-16.
Link-list Concept
The host and device controllers use link-list descriptors to manage transfers to and from memory
buffers. The concept is shown in Figure 15-5. The first Transfer Descriptors (TD) is pointed to by a
X-Ref Target - Figure 15-4
Figure 15-4: USB Endpoint Descriptors (device mode) and Schedules (host mode)
Endpoint Queue Heads
Endpoint 11 IN
EndPoint 0 IN
EndPoint 1 OUT
EndPoint 0 OUT
Device
Responds
to Host
Requests
Queue Head
List
Host Schedules (EHCI)
Queue Head a
Aysnchronous
Queue Heads
Queue Head b
Frame n Elements
Periodic Frame
List
Frame 3 Elements
Frame 1 Elements
Frame 2 Elements
Frame 0 Elements
dQH
FRINDEX pointer is advanced
for every USB Frame
Round Robin as
Bandwidth allows.
Programmable
number of
elements Insert and
Remove
QH’s as
needed
Maintain
Queue
Head List
Queue Head b
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