User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 40
UG585 (v1.11) September 27, 2016
Chapter 1: Introduction
1.4.2 PS-PL Interfaces
The PS-PL interface contains all the signals available to the PL designer for integrating the PL-based
functions and the PS. There are two types of interfaces between the PL and the PS.
1. Functional interfaces which include AXI interconnect, extended MIO interfaces (EMIO) for most
of the I/O peripherals, interrupts, DMA flow control, clocks, and debug interfaces. These signals
are available for connecting with user-designed IP blocks in the PL.
2. Configuration signals which include the processor configuration access port (PCAP),
configuration status, single event upset (SEU) and Program/Done/Init. These signals are
connected to fixed logic within the PL configuration block, providing PS control.
AXI functional interfaces:
•AXI_ACP
°
One 64-bit cache coherent master port in the PL
°
Connects to the snoop control unit for cache coherency between the CPUs and the PL
• AXI_HP, four high performance/bandwidth master ports in the PL
°
32-bit or 64-bit data master interfaces (independently programmed)
°
Efficient resizing in 32-bit slave interface configuration mode
°
Efficient upsizing to 64-bits for aligned 32-bit transfers in 32-bit slave interface
configuration mode
°
Automatic expansion to 64 bits for unaligned 32-bit transfers in 32-bit slave interface
configuration mode
°
Dynamic command upsizing translation between 32-bit and 64-bit interfaces, controllable
through AxCACHE[1]
°
Separate R/W programmable issuing capability for read and write commands
°
Programmable release threshold of write commands
°
Asynchronous clock frequency domain crossing for all AXI interfaces between the PL and PS
°
Smoothing out of “long-latency” transfers using 1 KB (128 by 64 bits) data FIFOs for both
reads and writes
°
QoS signaling available from PL ports
°
Command and data FIFO fill-level counts available to the PL
°
Standard AXI 3.0 interfaces supported
°
Large slave interface read acceptance capability in the range of 14 to 70 commands (burst
length dependent)
°
Large slave interface write acceptance capability in the range of 8 to 32 commands (burst
length dependent)
• AXI_GP, four general purpose ports
°
Two, 32-bit master interfaces
°
Two, 32-bit slave interfaces
°
Asynchronous clock frequency domain crossing for all AXI interfaces between the PL and PS
°
Standard AXI 3.0 interfaces supported