User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 402
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
The DMA engine is a 32-bit bus master on the AHB interface to access the PS system interconnect.
15.2.3 Protocol Engine
The protocol engine parses the USB tokens, generates response packets and performs error checking
functions. Data packets are passed through the transfer buffers, the DMA engine and system
memory.
The controller does not provide a hardware-based Transaction Translator for Low and Full speed
operations. Instead, the DMA and Protocol engines are used to support this functionality as
described in section 15.11.2 Embedded Transaction Translator.
X-Ref Target - Figure 15-7
Figure 15-7: USB DMA Controller Block Diagram
UG585_c15_36_030713
Control and Status Registers
DMA Traffic
Protocol
Engine
Port
Controller
* Burst Movement
* Bus State
* FIFO Arbitration
Traffic Context
Registers
DMA
Arbitrator
* Packet Movement
* Host: HS
* Device: HS and FS
ULPI
DMA Control
Host Mode:
* EHCI
* Scheduler
Device Mode:
* Prime/Unprime Control
* Endpoint Manager
* Context Storage Dual-port RAM
* Update Logic
DMA Context
* Byte Count ALU
* Address Incrementing
AHB
APB
Slave
Master
Tx FIFO
Rx FIFO
ULPI Link
Wrapper
Dual-port
RAM
PS Interconnect
PS Interconnect
X-Ref Target - Figure 15-8
Figure 15-8: USB Protocol Engine Block Diagram
UG585_c15_37_030713
Control and Status Registers
AHB
I/O Interface
APB
Protocol Engine Control
DMA
Controller
* Muxing / Pipelining
* FIFO Control
* CRC
Protocol Engine Data Path
Host:
* SOF Generation
* PID Generation
ULPI
Interval
Timers
* Generate Frame/MicroFrame
* Generate Scheduler Timing Strobes
Timebase Interval Timers
* Bus Timeout
* Inter-Packet Delay
Device:
* Prime Endpoint Logic
* PID Tracking
* Handshake Decision Logic
* Datapath Control
Port
Controller
Slave
Master
Tx FIFO
Rx FIFO
ULPI Link
Wrapper