User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 409
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
15.3.6 OTG Status/Interrupt and Control Register
The programming model for On-the-Go (OTG) USB is supported by the OTG status and control register
(OTGSC). The OTG operation works independently of the host and device modes. In OTG mode, once the
controller has determined which mode to operate in, the full features of that mode (host or device) are
available to the software.
Please refer to 15.14.2 OTG Interrupt and Control Bits.
15.4 Device Mode Control
When the controller is in device mode, software enables its control endpoint, prepares descriptors based
on the functionality of the device and prepares the necessary endpoints.
Table 15-2: USB Interrupt and Status Register Bits
USBSTS
(status)
Bit Field
Type
USBINTR
(enable)
Bit Field
Description
Dev Host
Cross Reference
[TI1]
25 Interrupt 25 Timer 1. xx
15.2.6 General Purpose Timers
[TI0]
24 Interrupt 24 Timer 0. xx
[UPI]
19 Interrupt 19 Periodic qTD complete. ~x
[UAI]
18 Interrupt 18 Async qTD complete. ~x
[NAKI]
16 Interrupt 16 Device generated NAK. x~
[AS]
15 Status-only na Async Schedule state. ~x
[PS]
14 Status-only na Periodic Schedule state. ~x
[RCL]
13 Status-only na Host Reclamation status. ~x
[HCH]
12 Status-only na Halt status of Run/Stop.
[ULPII]
10 Interrupt 10 ULPI Viewport transfer complete. xx
[SLI]
8 Interrupt 8 Device enters Suspend state. x~
[SRI]
7 Interrupt 7 Start of Frame (SOF) received. x~
Table 15-17
[URI]
6 Interrupt 6 Reset received. x~
[AAI]
5 Interrupt 5 Async schedule advance. ~x
[SEI]
4 Interrupt 4 System Error response on AHB. xx
[FRI]
3 Interrupt 3 Periodic Frame List rollover. ~x
[PCI]
2 Interrupt 2 Port Change Detect. xx
[UEI]
1 Interrupt 1 USB Transaction Error.
[UI]
0Interrupt 0TD complete x
Table 15-17