User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 411
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
As a result of entering the address state, the device address register (usb._DEVICEADDR) must be
programmed by the DCD.
Entry into the configured state indicates that all endpoints to be used in the operation of the device
have been properly initialized by programming the usb.ENDPTCTRLx registers and initializing the
associated queue heads.
15.4.2 USB Bus Reset Response
A USB bus reset is used by the host to initialize downstream devices. The USB reset is one of several
types of resets in the system, refer to section 15.15.2 Reset Types for a list.
When a bus reset is detected, the device controller hardware renegotiates its attachment speed,
reset the device address to 0 and notify the DCD by interrupt (assuming the USB reset interrupt
enable is set). After a reset is received, all endpoints (except EP 0) are disabled and any primed
transactions are canceled by the device controller. The concept of priming will be clarified below, but
the DCD must perform the following tasks when a reset is received.
DCD Actions
1. Clear all setup token semaphores by reading the usb.ENDPTSETUPSTAT register and writing the
same value back to the usb.ENDPTSETUPSTAT register. Clear all the endpoint complete status bits
by reading the usb.ENDPTCOMPLETE register and writing the same value back to the
usb.ENDPTCOMPLETE register.
2. Cancel all primed status by waiting until all bits in the usb.ENDPTPRIME register are 0 and then
writing FFFF_FFFFh to usb.ENDPTFLUSH register.
3. Read the reset bit in the PORTSC1 register and make sure that it is still active. A USB reset occurs
for a minimum of 3 ms and software must reach this point in the reset cleanup before end of the
reset occurs, otherwise a hardware reset of the device controller is recommended (rare).
Device Controller Reset
4. A hardware reset can be performed by writing a 1 to the usb.USBCMD [RST] reset bit. A hardware
reset will cause the device to detach from the bus by clearing the run/stop bit. Thus, software
must completely re-initialize the device controller after a hardware reset.
5. Free all allocated dTD’s because they will no longer be executed by the device controller. If this
is the first time the DCD is processing a USB reset event, then it is likely that no dTD’s have been
allocated.
At this time, the DCD might release control back to the OS because no further changes to the device
controller are permitted until a port change detect is indicated.
Table 15-3: USB Device State Information Bits
Bit Description Register Bit Interrupt
Suspend Mode usb.USBSTS [SLI] Yes
USB Reset Received usb.USBSTS [URI] Yes
Port Change Detect usb.USBSTS [PCI] Yes
High-Speed Port usb.PORTSC1 [PSPD] No