User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 414
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
15.5.2 Manage Endpoints
The USB 2.0 Specification defines an endpoint, also called a device endpoint or an address endpoint
as a uniquely addressable portion of a USB device that can source or sink data in a communications
channel between the host and the device. The endpoint address is specified by the combination of
the endpoint number and the endpoint direction.
The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint
0 for a device is always a control type data channel used for device discovery and enumeration. Other
types of endpoints support by USB include bulk, interrupt, and isochronous. Each endpoint type has
specific behavior related to packet response and error handling. More detail on endpoint operation
can be found in the USB 2.0 Specification.
The device controller hardware is configured to support up to 12 endpoints. The DCD can enable,
disable and configure endpoint type up to the maximum selected during synthesis.
Each endpoint direction is essentially independent and can be configured with differing behavior in
each direction. For example, the DCD can configure endpoint 1 IN to be a bulk endpoint and
endpoint 1 OUT to be an isochronous endpoint. This helps to conserve the total number of endpoints
required for device operation. The only exception is that control endpoints must use both directions
on a single endpoint number to function as a control endpoint. Endpoint 0, for example, is always a
control endpoint and uses the pair of directions.
Each endpoint direction requires a queue head allocated in memory. For 12 endpoints, numbers is
used, then 24 queue heads are required one for each endpoint direction being used by the device
X-Ref Target - Figure 15-14
Figure 15-14: USB Device Descriptor and Data Flow
DMA
Engine
System Memory
Rx and Tx
FIFOs
(Latency Buffers)
DMA
Protocol
Engine
Port
Controller
and ULPI
Link
Wrapper
ULPI
dTD
Read/Write
dQH
Read/Write
Dual-port RAM
Buffer
Pointers
Transfer Buffers
4KB each
Memory Buffers
EndPoint dTD
Next dTD
Pointers
dTD
Transfer Descriptors
Endpoint 11 IN
EndPoint 0 IN
EndPoint 1 OUT
EndPoint 0 OUT
usb.ENDPOINTLISTADDR [31:11]
dQH
0x040
0x600
0x080
0x5C0
0x0C0
0x000
Queue Head
List
dQH
dTD
Transfer
Overlay Area
(7 DWords)
31 0
Transaction Descriptor
Processor
USB Controller
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