User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 415
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
controller. The operation of an endpoint and use of queue heads are described later in this
document.
15.5.3 Endpoint Registers
The endpoint registers are listed in Table 15-4 USB Device Endpoint Register Summary. These
registers were summarized at the end of Table 15-1, page 407.
In general, there is one bit for each endpoint. The lower half of the register bits are for Rx endpoints
and the upper half is for Tx endpoints. Exceptions include the ENDPTSETUPSTAT and the endpoint
control registers, ENDPTCTRL{11:0}.
Endpoint Registers
Table 15-4: USB Device Endpoint Register Summary
Register Name
Description and Register Bit Field
Type
Tx Endpoint (11:0) Rx Endpoint (11:0)
ENDPTNAK
Bit is set when an endpoint sends a NAK to the Host. Read and
Write-one-to-clear.
[EPTN], 27:16
(IN token)
[EPRN], 11:0
(OUT or Ping token)
ENDPTNAKEN
Interrupt enable bits for ENDPTNAK bits. Read/Write.
[EPTNE], 27:16 [EPRNE], 11:0
ENDPTSETUPSTAT
Bit is set when an endpoint receives a Setup transaction. Read and
Write-one-to-clear.
~ [ENDPTSETUPSTAT], 11:0
ENDPTPRIME
Software sets a bit to instruct the controller to prepare for a
packet transfer. The QH, dTD’s, and endpoint registers are
ready.
Read and
Write-one-to-set.
[PETB], 27:16
(IN or Interrupt)
[PERB], 11:0
(OUT)
ENDPTFLUSH
Software sets a bit to instruct the controller to flush an
endpoint.
Read and
Write-one-to-set.
[FETB], 27:16 [FERB], 11:0
ENDPTSTAT
Indicates that the controller hardware has primed the endpoint
as requested by the ENDPTPRIME register.
Read-only.
[ETBR], 27:16 [ERBR], 11:0
ENDPTCOMPLETE
Indicates that the controller has completed the transfer that
was primed.
Read and
Write-one-to-clear.
[ETCE], 27:16 [ERCE], 11:0