User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 416
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Endpoint Configuration Registers
15.5.4 Endpoint Initialization
After hardware reset, all endpoints except endpoint 0 are uninitialized and disabled. The DCD must
configure and enable each endpoint by writing to the configuration register usb.ENDPTCTRLx. Each
32-bit usb.ENDPTCTRLx is split into an upper and lower half. The lower half of usb.ENDPTCTRLx
register is used to configure the receive or OUT endpoint and the upper half is likewise used to
configure the corresponding transmit or IN endpoint. Control endpoints must be configured the
same in both the upper and lower half of the usb.ENDPTCTRLx register otherwise the behavior is
undefined. Table 15-6 shows how to construct a configuration word for endpoint initialization.
Table 15-5: USB Device Endpoint Configuration Register Summary
Register Name
Description and Register Bit Field
Type
Tx Rx
ENDPTCTRL0
Software can control the STALL behavior for Rx and Tx
transactions to the control endpoint. Software can read the
control endpoint configuration.
(see below)
[TXS], 16 [RXS], 0 Read-write.
Others: always enabled, Tx and Rx capable. Read-only.
ENDPTCTRL {11:0}
Software configuration and control bits for each endpoint.
Refer to Table 15-6, page 416.
Read-write.
Force controller to send Stall responses.
[TXS], 16 [RXS], 0
Always set = 0 (datapath includes FIFOs).
[TXS], 17 [RXS], 1
Select endpoint type (Control, ISO, Bulk, Interrupt).
[TXS], 19:18 [RXS], 3:2
Always set = 0 (test mode to ignore data toggling).
[TXS], 21 [RXS], 5
Data toggle reset (write 1 to synchronize data PIDs).
Write-one.
[TXS], 22 [RXS], 6
Endpoint enable.
Read-write.
[TXS], 23 [RXS], 7
Table 15-6: USB Device Endpoint Initialization
Field Value Meaning
Data Toggle Reset, usb.ENDPTCTRLx [TXR] 1 Restart transfers with DATA0 PID.
Date Toggle Inhibit, usb.ENDPTCTRLx [TXI] 0 Toggle between DATA0 and DATA1 PIDs.