User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 417
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Stall
There are two occasions where the device controller might need to return a STALL to the host:
• Functional Stall: software initiated (non-control endpoints only).
• Protocol Stall: hardware initiates (control endpoint).
The functional stall, which is a condition set by the DCD as described in the USB 2.0 device
framework. A functional stall is only used on non-control endpoints and can be enabled in the device
controller by setting the usb.ENDPTCTRLx [TXS] stall bit associated with the given endpoint and the
given direction. In a functional stall condition, the device controller will continue to return STALL
responses to all transactions occurring on the respective endpoint and direction until the endpoint
stall bit is cleared by the DCD.
A protocol stall, unlike a function stall, is used on control endpoints and automatically cleared by the
device controller at the start of a new control transaction (setup phase). When enabling a protocol
stall, the DCD should enable the stall bits (both directions) as a pair. A single write to the
usb.ENDPTCTRLx register can ensure that both stall bits are set at the same instant.
Note: Any write to the usb.ENDPTCTRLx register during operational mode must preserve the
endpoint type field (i.e. perform a read-modify-write of this register and preserve the [TXT] field).
Data Toggle
Data toggle is a mechanism to maintain data ordering between the host and device for a given data
pipe. For more information on data toggle, refer to the USB 2.0 specification.
The DCD can reset the data toggle state bit and cause the data toggle sequence to reset in the device
controller by writing a 1 to the data toggle reset bit in the usb.ENDPTCTRLx [TXR] register bit. This
should only be necessary when configuring/initializing an endpoint or returning from a STALL
condition.
Endpoint Type, usb.ENDPTCTRLx [TXT] Depends on the
setup request.
00: Control
01: Isochronous
10: Bulk
11: Interrupt
Endpoint Stall, usb.ENDPTCTRLx [TXS] 0 Do not force stall response.
Table 15-7: USB Device Packet Mismatch Response
USB Packet Type
Received
Endpoint Type
Stall Bit setting
[TXS]
Hardware action
on Stall bit
Bus Response
Setup
Control x Clears [TXS] ACK
Non-Control x None STALL
IN/OUT/Ping
All 0 None ACK/NAK/NYET
All 1 None STALL
Table 15-6: USB Device Endpoint Initialization (Cont’d)
Field Value Meaning