User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 418
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Data Toggle Inhibit
This feature is for test purposes only and should never be used during normal device controller
operation. Setting the data toggle inhibit bit active (usb.ENTPTCTRLx [RXI] bit = 1) causes the device
controller to ignore the data toggle pattern that is normally sent and accept all incoming data
packets regardless of the data toggle state.
In normal operation, the device controller checks the DATA0/DATA1 bit against the data toggle to
determine if the packet is valid. If Data PID does not match the data toggle state bit maintained by
the device controller for that endpoint, the Data toggle is considered not valid. If the data toggle is
not valid, the device controller assumes the packet was already received and discards the packet (not
reporting it to the DCD). To prevent the host controller from re-sending the same packet, the device
controller will respond to the error packet by acknowledging it with either an ACK or NYET response.
15.6 Device Endpoint Packet Operational Model
All transactions on the USB bus are initiated by the host and in turn, the device must respond to any
request from the host within the turnaround time stated in the USB 2.0 Specification. At USB 1.1 Full
or Low Speed rates, this turnaround time was significant and the USB 1.1 device controllers were
designed so that the device controller could access main memory or interrupt a host protocol
processor in order to respond to the USB 1.1 transaction. The architecture of the USB 2.0 device
controller must be different because the same methods will not meet USB 2.0 High-speed
turnaround time requirements.
A USB host sends requests to the device controller in an order that cannot be precisely predicted as
a single pipeline, so it is not possible to prepare a single packet for the device controller to execute.
However, the order of packet requests is predictable when the endpoint number and direction is
considered. For example, if endpoint 3 (transmit direction) is configured as a bulk pipe, then we can
expect the host will send IN requests to that endpoint.
Prime and Flush Endpoints
This device controller is designed in such a way that it can prepare packets for each endpoint or
direction in anticipation of the host request. The process of preparing the device controller to send
or receive data in response to host initiated transaction on the bus is referred to as ‘priming’ the
endpoint. The term ‘flushing’ is used to describe the action of clearing a packet that was queued for
execution.
15.6.1 Prime Transmit Endpoints
Priming a transmit endpoint will cause the device controller to fetch the dTD for the transaction
pointed to by the dQH. After the dTD is fetched, it will be copied in the dQH until the device
controller completes the transfer described by the dTD. Copying the dTD in the dQH overlay area
allows the device controller to fetch the operating context needed to handle a request from the host
without the need to follow the linked list, starting at the dQH when the host request is received.