User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 422
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
15.6.4 Isochronous Endpoint Operational Model
Isochronous endpoints are used for real-time scheduled delivery of data and their operational model
is significantly different than the host throttled bulk, interrupt, and control data pipes. Real time
delivery by the device controller is accomplished by the following:
• Exactly MULT Packets per (micro)frame are transmitted/received.
Note: MULT is a two-bit field in the device queue head. The variable length packet protocol is
not used on isochronous endpoints.
• NAK responses are not used. Instead, zero length packets are sent in response to an IN request
to an unprimed endpoints. For unprimed Rx endpoints, the response to an OUT transaction is to
ignore the packet within the device controller.
• Prime requests always schedule the transfer described in the dTD for the next (micro)frame. If
the ISO-dTD is still active after that frame, then the ISO-dTD is held ready until executed or
canceled by the DCD.
Note: If the MULT field is set to more packets than present in the dTD to be transmitted, the
controller sends zero length packets to all extra incoming IN tokens and report fulfillment error
(transaction error) in current dTD. If more dTD’s exist in memory, the controller moves to the next
dTD to be transmitted in the next (micro)frame. Because of this behavior it is recommended to
always use the correct MULT matching the number of packets to be processed for a given dTD.
An EHCI compatible host controller uses the periodic frame list to schedule data exchanges to
Isochronous endpoints. The operational model for the device controller does not use such a data
structure. Instead, the same dTD used for Control/Bulk/Interrupt endpoints is also used for
isochronous endpoints. The difference is in the handling of the dTD.
The first difference between bulk and iso endpoints is that priming an iso endpoint is a delayed
operation such that an endpoint will become primed only after a SOF is received. After the DCD
writes the prime bit, the prime bit will be cleared as usual to indicate to the DCD that the device
controller completed a priming the dTD for transfer. Internal to the design, the device controller
hardware masks that prime start until the next frame boundary. This behavior is hidden from the DCD
but occurs so that the device controller can match the dTD to a specific (micro)frame.
Another difference with isochronous endpoints is that the transaction must wholly complete in a
(micro)frame. Once an isochronous transaction is started in a (micro)frame it will retire the
Invalid Ignore Ignore Ignore Ignore Ignore BTO
Notes:
1. BS Error — Force Bit Stuff Error.
2. NYET/ACK — NYET unless the Transfer Descriptor has packets remaining according to the USB variable length
protocol then ACK.
3. SYSERR — System error should never occur when the latency FIFOs are correctly sized and the DCD is
responsive.
4. BTO — Bus Time Out.
Table 15-9: USB Device Interrupt and Bulk Endpoint Bus Response (Cont’d)
Packet
Identifier
Stall Bit
[TXS]
Endpoint
Not Primed
Endpoint
Primed
Buffer
Underflow
Buffer
Overflow
Endpoint
Not Enabled