User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 424
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Isochronous Pipe Synchronization
When it is necessary to synchronize an isochronous data pipe to the host, the (micro)frame number
(read the FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific
(micro)frame number [N], the DCD should interrupt on SOF during frame N - 1. When the FRINDEX
= N - 1, the DCD must write the prime bit. The device controller primes the isochronous endpoint in
(micro)frame N - 1 so that the device controller executes delivery during (micro)frame N.
Caution: Priming an endpoint towards the end of (micro)frame N - 1 does not guarantee delivery in
(micro)frame N. The delivery might actually occur in (micro)frame N+1 if device controller does not
have enough time to complete the prime before the SOF for packet N is received.
Isochronous Endpoint Bus Response
15.6.5 Control Endpoint Operational Model
All requests to a control endpoint begin with a setup phase followed by an optional data phase and
a required status phase. The device controller always accepts the setup phase unless the setup
lockout is engaged.
Lockout and Tripwire for Setup Packets
The setup lockout can be engage so that future setup packets from the host are ignored by the
controller while the DCD retrieves the current setup packet. Lockout of setup packets ensures that
while the DCD is reading the setup packet stored in the queue head data is not written as it is being
read potentially causing an invalid setup packet.
The setup lockout mechanism can be disabled and a tripwire type semaphore will ensure that the
setup packet payload is extracted from the queue head without being corrupted by an incoming
setup packet. This is the preferred behavior because ignoring repeated setup packets due to long
software interrupt latency would be a compliance issue.
The tripwire semaphore can ensure the proper addition of a new dTD to an active (primed)
endpoint’s linked list. The add dTD tripwire bit, usb.USBCMD [ATDTW] can be set and cleared by
software. This bit can be cleared by hardware when its state machine is in a hazard region for which
adding a dTD to a primed endpoint may go unrecognized.
Table 15-10: USB Device Isochronous Endpoint Bus Response
Token Type
Stall Bit
[TXS]
Endpoint
Not Primed
Endpoint
Primed
Buffer
Underflow
Buffer
Overflow
Endpoint
Not Enabled
Setup STALL STALL STALL N/A N/A BTO
IN NULL Packet NULL Packet
Transmit BS Error N/A BTO
OUT Ignore Ignore
Receive N/A Drop Packet BTO
Ping Ignore Ignore Ignore Ignore Ignore BTO
Invalid Ignore Ignore Ignore Ignore Ignore BTO