User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 425
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Setup Packet Handling using the Tripwire
Disable setup lockout by writing 1 to setup lockout mode, usb.USBMODE [SLOM] bit field; once at
initialization. Setup lockout is not necessary when using the tripwire as described in the example
below.
Example: Setup Packet Handing using the Tripwire
After receiving an interrupt and inspecting usb.ENDPTSETUPSTAT register to determine that a setup
packet was received on a particular pipe (i.e., the dQH was written to memory by the hardware):
1. Setup the Tripwire Mechanism: Write 1 to usb.USBCMD [SUTW].
2. Read the Setup Buffer: Copy the contents of dQH.SetupBuffer into local software byte array.
3. Test to see if another Setup Packet was received. Read the tripwire bit [SUTW] again.
a. If [SUTW] = 1 (not received), then continue to step 4 and process the setup buffer.
b. If [SUTW] = 0 (another packet received), then go to step 1 and copy that setup buffer, too.
4. Clear the Interrupt: Write 1 to clear corresponding usb.ENDPTSETUPSTAT register bit.
A poll loop should be used to wait until usb.ENDPTSETUPSTAT transitions to 0 and before
priming for the status/handshake phases.
The time from writing a 1 to usb.ENDPTSETUPSTAT register and reading back a 0 is very short
(approximately 1 to 2 microsecond) so a poll loop in the DCD should not be harmful in most
systems.
5. Clear the Tripwire: Write 0 to clear setup tripwire bit usb.USBCMD [SUTW].
6. Process setup packet: Use the local software byte array copy and execute status/handshake
phases.
7. Check Endpoint status: Before priming for status/handshake phases, ensure that the
usb.ENDPTSETUPSTAT bit is = 0.
Note: After receiving a new setup packet, the status and/or handshake phases might still be
pending from a previous control sequence. These should be flushed and deallocated before linking
a new status and/or handshake dTD for the most recent setup packet.
Data Phase
Following the setup phase, the DCD must create a device transfer descriptor for the data phase and
prime the transfer.
After priming the packet, the DCD must verify a new setup packet has not been received by reading
the usb.ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime
completes when the associated bit in the usb.ENDPTPRIME register is 0 and the associated bit in the
usb.ENDPTSTATUS register is a 1. If a prime fails, i.e., the usb.ENDPTPRIME bit goes to 0 and the
usb.ENDPTSTATUS bit is not set, then the prime has failed. This can only be due to improper setup of
the dQH, dTD or a setup arriving during the prime operation. If a new setup packet is indicated after
the endpoint prime bit is cleared, then the transfer descriptor can be freed and the DCD must
reinterpret the setup packet.