User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 426
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Should a setup arrive after the data stage is primed, the device controller automatically clears the
prime status (usb.ENDPTSTATUS) to enforce data ordering with the setup packet.
Note: The dQH.Mult field must be set to 00 for bulk, interrupt, and control endpoints. Error
handling of data phase packets is the same as bulk packets described previously.
Status Phase
Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal 0) and
prime the endpoint for the status phase. The DCD must also perform the same checks of the
usb.ENDPTSETUPSTAT as described above in the data phase.
Note: The dQH.Mult bit field must be set to 00 for bulk, interrupt, and control endpoints. Error
handling of data phase packets is the same as bulk packets described previously.
Control Endpoint Bus Response
The device controller response to packets on a control endpoint according to the device controller
state is shown in Table 15-11. The normal operating mode is shaded.
15.7 Device Endpoint Descriptor Reference
This section contains the definitions of the endpoint descriptors for the device controller. There
usages are described in other chapter sections, including section 15.5.1 Link-list Endpoint
Descriptors.
• 15.7.1 Endpoint Queue Head Descriptor (dQH)
• 15.7.2 Endpoint Transfer Descriptor (dTD)
Table 15-11: USB Device Control Endpoint Bus Response
Packet
Identifier
Stall Bit
[TXS]
Endpoint
Not Primed
Endpoint
Primed
Buffer
Underflow
Buffer
Overflow
Endpoint
Not Enabled
Setup
Lockout
Setup ACK ACK ACK N/A SYSERR BTO
IN STALL NAK Transmit BS Error N/A BTO N/A
OUT STALL NAK
Receive and
then
NYET/ACK
N/A NAK BTO N/A
Ping STALL NAK
ACK N/A N/A BTO N/A
Invalid Ignore Ignore Ignore Ignore Ignore BTO Ignore
Notes:
1. BS Error — Force Bit Stuff Error.
2. NYET/ACK — NYET unless the Transfer Descriptor has packets remaining according to the USB variable length
protocol then ACK.
3. SYSERR — System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive.
4. BTO — Bus Time Out.