User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 430
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Multiplier Override (MultO) Bit Field
The total bytes field is used for both dQH and dTD descriptors and is also used for transmit iso IN
endpoints to override the multiplier in the dQH. This field must be 0 for all packet types that are not
transmit (IN) iso endpoints. For maximal efficiency, the DCD should compute MultO = greatest
integer of (Total Bytes / Max. Packet Size) except for the case when Total Bytes = 0; then MultO
should be set = 1.
Example 1: Send three packets
• If dQH.multiplier = 3; Max packet size = 8; Total Bytes = 15; dQH.Mult = 0 (default),
then three packets are sent: Data2 (8) + Data1 (7) + Data0 (0).
Total Bytes, MultO, and Status.
13
31 Reserved. Field reserved and should be set to 0.
30:16 Total Bytes. Total number of bytes to be moved with this transfer descriptor. Refer to
section Total Bytes to Transfer Parameter for more info.
15 Interrupt On Complete, IOC. Indicates if USBINT is to be set in response to device
controller being finished with this dTD.
14:12 Current Page, C_Page. Reserved in Device mode.
11:10 Multiplier Override, MultO. Used for transmit isochronous packets, refer to text.
9:8 Reserved. Field reserved and should be set to 0.
7:0 Status. This field is used by the device controller to communicate individual command
execution status back to the DCD. This field contains the status of the last transaction
performed on this dTD. Bit [7] Active Status. Bit [6] Halted Status.
Bit [5] Data Buffer Error Status. Bit [3] Transaction Error Status.
Other bits: reserved.
Buffer Pointer Page 0 and Current Offset
24
31:12 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12].
11:0 Current Offset.
Frame Number and Buffer Pointer Page 1
35
31:12 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12].
11 Reserved, R. Field reserved and should be set to 0.
10:0 Frame Number. Written by the device controller to indicate the frame number in which
a packet finishes. This is typically used to correlate relative completion times of packets
on an iso endpoint.
Buffer Pointer Pages 2 to 4
4 to 6 6 to 8
31:12 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12].
11:0 Reserved. Field reserved and should be set to 0.
Table 15-15: USB Device Transfer Overlay (Cont’d)
Bits Description
dTD
DWord
dQH
DWord