User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 431
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Example 2: Send two packets
• If dQH.multiplier = 3; Max packet size = 8; Total Bytes = 15; dQH.Mult = 2,
then two packets are sent: Data1 (8) +Data0 (7).
Buffer Pointer Pages
The buffer pointers are aligned to 4KB boundaries. The total byes and buffer pointers are discussed
in section Total Bytes to Transfer Parameter.
Total Bytes to Transfer Parameter
The Total Bytes bit field specifies the total number of bytes to be moved with the transfer descriptor.
This field is decremented by the number of bytes actually moved during the transaction and only on
the successful completion of the transaction. This bit field applies to:
• qTD for host mode, refer to section 15.12.5 Queue Element Transfer Descriptor (qTD).
• dTD for device mode, refer to section 15.7.2 Endpoint Transfer Descriptor (dTD).
The maximum value that the DCD may store in the field is 5 times 4 KB (5000h). This is the maximum
number of bytes that 5 page pointers can reference. Although it is possible to create a transfer up to
20 KB this assumes the 1st offset into the first page is 0. When the offset cannot be predetermined,
crossing past the 5th page can be guaranteed by limiting the total bytes to 16 KB. Therefore, the
maximum recommended transfer is 16 KB (4000h).
Device Mode Note
If the value of the Total Bytes bit field is 0 when the device controller fetches this transfer descriptor
(and the active bit is set), the reaction of the device controller depends on the setting of the dQH.ZLT
bit. Refer to section 15.6.3 Interrupt and Bulk Endpoint Operational Model.
• It is not a requirement for that Total Bytes To Transfer be an even multiple of Maximum Packet
Length. If the DCD builds such a transfer descriptor for a transfer, the last transaction will always
be less that Maximum Packet Length.
15.8 Programming Guide for Device Controller
The function of the device controller is to transfer a request in the memory image to and from the
USB. The device controller programs and primes the endpoints based on the application protocol.
The controller executes a set of linked list transfer descriptors, pointed to by a queue head that the
device controller executes to perform the requested data transfers. The following sections explain
the use of the device controller from the DCD point-of-view and further describe how specific USB
bus events relate to status changes in the device controller’s registers.