User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 432
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
15.8.1 Software Model
The USB device controller API software provides a framework of routines to control the USB
controller in device applications. The software should be designed to significantly simplify the
software tasks required to develop a USB device application. The API software presents a high-level
data transfer interface to the user's application code. All the register, interrupt and DMA interactions
with the controller are managed by the API. The API also includes routines that handle all the USB
device framework commands which are required for all USB devices.
15.8.2 USB Reset
After receiving a USB reset from the bus, the port enters the default FS or default HS state in
accordance with the reset protocol described in Appendix C.2 of the USB Specification Rev. 2.0. The
state diagram shown in Figure 15-12 depicts the state of the controller in device mode.
15.8.3 Register Controlled Reset
To reset the controller, the DCD writes a 1 to the usb.USBCMD [RST] bit. When the reset process is
completed, the controller hardware sets this bit to 0. Once the reset is started, the controller cannot
stop the process. Writing a 0 has no effect.
Writing a 1 to the [RST] bit will reset the internal pipelines, timers, counters, and state machines to
their initial value. Writing a 1 when the device is in the attached state is not recommended since the
effects on an attached host are undefined. In order to ensure that the device is not in an attached
state, all primed endpoints should be flushed and the usb.USBCMD [RS] bit should be set to 0.
15.9 Programming Guide for Device Endpoint Data
Structures
This section describes how to manage the device endpoint data structures. These are images written in
system memory that are accessed by the controller to service USB transaction initiated by the host. These
structures are the basis for the device controller functions.
15.9.1 Device Controller Initialization Overview
After hardware reset, the device is disabled until the Run/Stop bit is set to a 1. In the disabled state,
the pull-up on the USB D+ is not active which prevents an attach event from occurring. At a
minimum, it is necessary to have the queue heads setup for endpoint 0 before the device attach
occurs. Shortly after the device is enabled, a USB reset occurs followed by setup packet arriving at
endpoint 0. A Queue head must be prepared so that the device controller can store the incoming
setup packet.
In order to initialize a device, the DCD should perform the following steps: