User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 433
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
1. Set the controller to device mode. Write 10 to the usb.USBMODE [CM] bit.
°
Transitioning from host mode to device mode requires a device controller reset before
modifying USBMODE.
°
Set usb.OTGSC [OT] bit = 1.
2. Allocate and initialize dQH’s.
°
Minimum: Initialize dQH’s for endpoint 0 for Tx and Rx.
°
All control endpoint queue heads must be initialized before the control endpoint is enabled.
Non-control queue heads must be initialized before the endpoint is used and not
necessarily before the endpoint is enabled.
°
For information on device queue heads, refer to section 15.7.1 Endpoint Queue Head
Descriptor (dQH).
3. Configure the Endpoint List Address. Write the memory address for the Queue Head endpoint
list into the usb._ENDPOINTLISTADDR [31:11] bit field.
4. Enable the software interrupt.
°
Enable IRQ interrupt signal in GIC (ID#53 for USB 0 and ID#76 for USB 1).
°
Enable device interrupts in the usb.USBINTR register:
- USB interrupt [UI]
- USB Error Interrupt [UEI]
- Port change detect [PCI]
-USB Reset received [URI]
- DCSuspend [SLI]
°
For a list of available interrupts refer to Table 15-2 USB Interrupt and Status Register Bits.
5. Enable Run mode. Set Run/Stop bit to Run Mode.
°
After the run bit is set, a device USB reset occurs. The DCD must monitor the reset event and
adjust the DCD state as described in the Bus Reset section of the following Port State and
Control section below.
°
Endpoint 0 is designed as a control endpoint only and does not need to be configured using
ENDPTCTRL0 register.
°
It is also not necessary to initially prime Endpoint 0 because the first packet received will
always be a setup packet. The contents of the first setup packet will require a response in
accordance with USB device framework (Chapter 9) command set.
15.9.2 Manage Transfer Descriptors
The function of the endpoint is to instruct the DMA engine to move data between system memory
and the Tx and Rx FIFOs. Each endpoint has two data structures: one for IN and the other for OUT
data transfers. The device mode data structures include a device Queue Head (dQH) and one or more
device Transfer Descriptors (dTD). The dQH defines the type of data transfer and points to the first
dTD. The dTD includes a system address pointer to the memory buffer(s) where data is either stored
or read from.