User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 434
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
The dQH’s are indexed (two for each endpoint) in the 24-element Endpoint Queue Head List. To
setup a transfer, software constructs the dQH and dTD(s) for an IN or OUT operation. Software must
maintain a consistent set of descriptors, schedules/lists, and data buffers in system memory for the
controller. When the endpoint is ready to receive or send the data, software primes the endpoint.
When an endpoint is primed, the device controller reads the associated dQH and dTD into the
controller’s dual-port RAM for easy access by the DMA and protocol engines. When the DMA for a
dTD is done, the controller writes the dTD back to system memory with transfer results (status). If the
terminate bit, T = 0 (do not terminate) then the controller fetches and processes the next dTD from
system memory. If T = 1, then the controller stops processing the endpoint dQH and writes the dQH
back to system memory.In a long link-list the controller will repeatedly cause the controller to read
and write dTD’s between system memory the controller’s dual-port RAM.
Example: Initialize dQH
One pair of device queue heads must be initialized before an endpoint is primed to respond to the
host. To initialize a device queue head (dQH):
1. Write the wMaxPacketSize field as required by the USB specification Chapter 9 or application
specific protocol.
2. Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For IsoUSB endpoints,
set the multiplier to 1, 2, or 3 as required bandwidth and in conjunction with the USB Chapter 9
protocol. Note: In FS mode, the multiplier field can only be 1 for IsoUSB endpoints.
3. To terminate the Transfer: Set T = 1 in the Terminate bit of the next dTD.
4. Write the Active bit in the status field to 0.
5. Write the Halt bit in the status field to 0.
Note: The DCD must only modify dQH if the associated endpoint is not primed and there are no
outstanding dTD's.
Example: Operational Model for Setup Transfers
As discussed in 15.6.5 Control Endpoint Operational Model, setup transfer requires special
treatment by the DCD. A setup transfer does not use a dTD but instead stores the incoming data from
a setup packet in an 8-byte buffer within the dQH.
1. Copy setup buffer contents from dQH - Rx to software buffer.
2. Acknowledge setup packet by writing a 1 to the corresponding bit in usb.ENDPTSETUPSTAT.
a. The acknowledge must occur before continuing to process the setup packet.
b. After the acknowledge has occurred, the DCD must not attempt to access the setup buffer in
the dQH - Rx. Only the local software copy should be examined.
3. Check for pending data or status dTD's from previous control transfers and flush if any exist as
discussed in section Flushing/De-priming an Endpoint.
a. It is possible for the device controller to receive setup packets before previous control
transfers complete. Existing control packets in progress must be flushed and the new control
packet completed.