User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 436
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
If 0 go to step 3.
If 1 continue to step 6.
6. Write usb.USBCMD [ATDTW] bit = 0.
7. If status bit read in (4) is 1 DONE.
8. If status bit read in (4) is 0 then Goto Case 1: step 1.
Transfer Completion
After a dTD has been initialized and the associated endpoint primed the device controller will
execute the transfer upon the host-initiated request. The DCD will be notified with a USB interrupt if
the interrupt on complete bit was set or alternately, the DCD can poll the endpoint complete register
to find when the dTD had been executed. After a dTD has been executed, the DCD can check the
status bits to determine success or failure.
Caution: Multiple dTD can be completed in a single endpoint complete notification. After clearing
the notification, the DCD must search the dTD linked list and retire all dTD’s that have finished
(Active bit cleared).
By reading the status fields of the completed dTD’s, the DCD can determine if the transfers
completed successfully. Success is determined with the following combination of status bits:
Active = 0
Halted = 0
Transaction Error = 0
Data Buffer Error = 0
Should any combination other than the one shown above exist, the DCD must take proper action.
Transfer failure mechanisms are indicated in the device error matrix.
In addition to checking the status bit, the DCD must read the Transfer Bytes field to determine the
actual bytes transferred. When a transfer is complete, the Total Bytes transferred is decremented by
the actual bytes transferred. For Transmit packets, a packet is only complete after the actual bytes
reach 0, but for receive packets, the host might send fewer bytes in the transfer according the USB
variable length packet protocol.
Example: Flushing/De-priming an Endpoint
It is necessary for the DCD to use the flush bit(s) to de-prime one or more endpoints when a USB
device reset is received or when a broken control transfer occurs. There can also be application
specific requirements to stop transfers in progress. The following procedure can be used by the DCD
to stop a transfer in progress and ensure the transfer has stopped:
1. Write a 1 to the corresponding bit(s) in usb.ENDPTFLUSH.
2. Wait until all bits in usb.ENDPTFLUSH are 0.
Software interrupt routine note: This operation can take a large amount of time depending on
the USB bus activity. It is not desirable to have this wait loop within an interrupt service routine.
3. Read usb.ENDPTSTAT to ensure that for all endpoints commanded to be flushed, that the
corresponding bits are now 0. If the corresponding bits are 1 after step #2 has finished, then the