User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 437
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
flush failed: in very rare cases, a packet is in progress to the particular endpoint when
commanded flush using usb.ENDPTFLUSH. A safeguard is in place to refuse the flush to ensure
that the packet in progress completes successfully. The DCD might need to repeatedly flush any
endpoints that fail to flush be repeating steps 1–3 until each endpoint is successfully flushed.
Note: A time out counter can be programmed to recover from when an endpoint flush fails.
Device Errors
Table 15-16 summarizes packet errors that are not automatically handled by the device controller.
Notice that the device controller handles all errors on Bulk/Control/Interrupt Endpoints except for a
data buffer overflow. However, for IsoUSB endpoints, errors packets are not retried and errors are
tagged as indicated.
15.9.4 Service Device Mode Interrupts
Note: The interrupt service routine must consider that there are high-frequency, low-frequency
operations, and error interrupts. It is likely that multiple interrupts will stack up on a call to the
Interrupt Service Routine (ISR) and then during the execution of the interrupt service routine.
The interrupt handling strategy is up to the user. The ISR can poll the high-frequency and then
low-frequency interrupts before exiting. If another interrupt is detected and processed, then the ISR
would perform another ‘last scan’ of the interrupts before exiting.
High-Frequency Interrupts
High frequency interrupts, in particular, should be handed in the order shown in Table 15-17. The
most important of these are the first two, 1a and 1b. They have equal priority because the software
Table 15-16: USB Device Errors
Error Direction
Packet
Type
Data Buffer
Error Bit
(dTD.Status
bit 5)
Transaction
Error Bit
(dTD.Status
bit 3)
Description
Overflow Rx Any 10
Number of bytes received exceeded max. packet size or
total buffer length. This error will also set the Halt bit in
the dQH and if there are dTD’s remaining in the linked
list for the endpoint, then those will not be executed.
Isochronous
Packet
Rx Iso 01
CRC Error on received isochronous packet. Contents not
guaranteed to be correct.
Isochronous
Fulfillment
Both Iso 01
Host failed to complete the number of packets defined
in the dQH.Mult field within the given (micro)frame. For
scheduled data delivery the DCD might need to readjust
the data queue because a fulfillment error will cause
Device Controller to cease data transfers on the pipe for
one (micro)frame. During the “dead” (micro)frame, the
Device Controller reports error on the pipe and primes
for the following frame.