User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 440
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
• Isochronous split transaction data streams are managed with split-transaction isochronous
transfer descriptors (siTD).
• Interrupt, Control, and Bulk data streams are managed via queue heads (QH) and queue
element transfer descriptors (qTD). These data structures are optimized to reduce the total
memory footprint of the schedule and to reduce (on average) the number of memory accesses
needed to execute a USB transaction.
15.10.2 Periodic Schedule
The periodic schedule provides interrupt and isochronous transfers by using the Periodic Frame list
of elements and transfer descriptors as shown in Figure 15-15.
Periodic Frame List
The host controller uses the Periodic Frame List to schedule isochronous and interrupt transfers. The
periodic frame list is written into memory by the HCD. The host controller hardware reads the
elements using the usb.PERIODICLISTBASE_ base address and the FRINDEX index registers. The
current element within the periodic frame list is pointed to by the FRINDEX register. The Periodic
Frame List implements a sliding window of work over time.
Note: The periodic frame list is a 4 KB page-aligned array for pointers to Isochronous and interrupt
transfer descriptors. The length of the frame list is programmable: 8, 16, 32, 64, 128, 256, 512, or
1024 elements using the usb.USBCMD [FS2] and [FS0] bit fields. When [FS2] is set = 0, then the EHCI
programming model: 256, 512 and 1024 elements can be used in [FS0]. The length of the frame list
affects the amount of system memory to allocate and the number of periodic transactions that can
be queued.
The HCD writes the memory address of the first element in the periodic frame list in the
usb.PERIODICLISTBASE_ [PERBASE_] bit field. The controller beings processing the periodic frame list
when the (micro)frame time stamp occurs.
X-Ref Target - Figure 15-15
Figure 15-15: USB Host Periodic Schedule with Example
UG585_c15_43_030713
Periodic Frame
List (EHCI)
Frame 3 Elements
Frame 1 Elements
Frame 2 Elements
Frame 0 Elements
advanced for every
USB Frame.
Programmable
number of elements:
8, 16, 32, … 1024.
Programmed by
usb.USBCMD [FS2] [FS0]
usb.PERIODLISTBASE_ [31:12]
Periodic Frame List
Element Address
(32-bit system address)
usb.FRINDEX
000
Frame 7 Elements
Frame 5 Elements
Frame 6 Elements
Frame 4 Elements
Frame 8 Elements
Interrupt QH executed
every 8 Frames
Interrupt QH executed
every 4 Frames
Interrupt QH executed
every Frame
Isochronous
Transfer
Descriptors
Last QH has terminate
bit set, T = 1.
Link Pointer
Link Pointer
Example