User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 447
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
2. Reset the device. Writes a 1 to the usb.PORTSC1 [PR] bit. assumes the
3. Optional Step to de-assert Reset. The HCD normally writes a 0 to the [PR] bit to de-assert the
reset after 10 ms. This step, which is necessary in a standard EHCI design, can be omitted. Should
the EHCI HCD attempt to write a 0 to the reset bit while a reset is in progress, the write is ignored
and the reset continues until completion.
4. Wait for device to be operational. Receive the [PCI] interrupt to indicate the Port Enable
Change. The device is now operational and at this point the port speed has been determined.
15.11.5 Port Speed Detection Mechanism
After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the
port speed. Unlike the EHCI implementation which re-assign the port owner for any device that does
not connect at High-Speed, this host controller supports direct attach of non High-Speed devices.
Therefore, the following differences are important regarding port speed detection:
• Port owner is read-only and always reads 0.
• A 2-bit port speed indicator (PSPD) has been added to PORTSC1 to provide the current
operating speed of the port to the HCD.
• A 1-bit High Speed indicator (HSP) has been added to PORTSC1 to signify that the port is in
High-Speed vs. Full/Low Speed - This information is redundant with the 2-bit Port Speed
indicator above.
15.11.6 FS/LS Data Structures
The data structures used by the TT for FS/LS transactions are similar to an HS hub. The hub address
and endpoint speed fields should be set for directly attached FS/LS devices and hubs:
• QH (FS/LS)- Asynchronous (Bulk and Control endpoints) and Periodic (Interrupt endpoint)
°
Hub Address = TTHA (default TTHA = 0)
°
Transactions to directly attached device or hub.
-QH.EPS = Port Speed (for both FS and LS)
°
Transactions to a device downstream from direct attached HS hub.
- QH.EPS = Downstream Device Speed
°
Maximum Packet Size must be less than or equal 64 or undefined behavior might result.
°
When QH.EPS = 01 (LS) and usb.PORTSC1 [PSPD] = 00 (FS), a LS-pre-PID will be sent before
the transmitting LS traffic.
• siTD (FS) - Periodic (ISO endpoint)
°
All FS IsoUSB transactions:
- Hub Address = (default TTHA = 0)
-siTD.EPS = 00 (full speed)
°
Maximum Packet Size must less than or equal to 1023 or undefined behavior might result.
Note: FSTN data structures are used for FS and LS devices that are downstream of a high speed hub
(not when FS or LS device is connected directly to the host controller.)