User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 448
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
15.11.7 Operational Model of the TT
The operational models are well defined for the behavior of the transaction translator (see USB 2.0
specification) and for the EHCI controller to move packets between system memory and a USB-HS
hub. Since the transaction translator exists within the host controller there is no physical bus
between EHCI HCD and the USB FS/LS bus. These sections briefly discuss the operational model for
how the EHCI and transaction translator operational models are combined without the physical bus
between. The following sections assume the reader is familiar with both the EHCI and USB 2.0
transaction translator operational models.
Microframe Pipeline
The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline
between the Host (H) and the Bus (B). The embedded transaction translator shall use the same
pipeline algorithms specified in the USB 2.0 specification for a Hub-based Transaction Translator.
All periodic transfers always begin at B-frame 0 (after SOF) and continue until the stored periodic
transfers are complete. As an example of the microframe pipeline implemented in the embedded
transaction translator, all periodic transfers that are tagged in EHCI to execute in H-frame 0 will be
ready to execute on the bus in B-frame 0.
It is important to note that when programming the S-mask and C-masks in the EHCI data structures
to schedule periodic transfers for the embedded transaction translator, the EHCI HCD must follow
the same rules specified in EHCI for programming the S-mask and C-mask for downstream
hub-based transaction translators.
Once periodic transfers are exhausted, any stored asynchronous transfer will be moved.
Asynchronous transfers are opportunistic in that they shall execute whenever possible and their
operation is not tied to Hframe and B-frame boundaries with the exception that an asynchronous
transfer cannot babble through the SOF (start of B-frame 0.)
Split Transfer State Machines
When the controller attaches to a downstream FS/LS device via an HS hub, the controller can initiates
split transfers to allow for traffic to other devices to be intertwined.
The start and complete split operational model differs from EHCI slightly because there is no bus
medium between the EHCI controller and the embedded transaction translator. Where a start or
complete-split operation would occur by requesting the split to the HS hub, the start/complete split
operation is simple an internal operation to the embedded transaction translator. Table 15-22
summarizes the conditions where handshakes are emulated from internal state instead of actual
handshakes to HS split bus traffic.
Table 15-22: USB Handshake Emulation Conditions
Condition TT Response
Start-Split: All asynchronous buffers full. NAK
Start-Split: All periodic buffers full. ERR
Start-Split: Success for start of async. transaction. ACK