User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 449
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
Asynchronous Transaction Scheduling and Buffer Management
The following USB 2.0 specification items are implemented in the Transaction Translator:
USB 2.0 - 11.17.3Sequencing is provided and a packet length estimator ensures
no full-speed/low-speed packet babbles into SOF time.
USB 2.0 - 11.17.4Transaction tracking for 2 data pipes.
USB 2.0 - 11.17.5Clear_TT_Buffer capability provided through the use of the
TTCTRL register.
Periodic Transaction Scheduling and Buffer Management
The following USB 2.0 specification items are implemented in the transaction translator:
USB 2.0 - 11.18.6.[1-2]Abort of pending start-splits
- EOF (and not started in microframes 6)
- Idle for more than 4 microframes (Abort of pending complete-splits)
-EOF
- Idle for more than 4 microframes
USB 2.0 - 11.18.[7-8]Transaction tracking for up to 16 data pipes.
Caution: Limiting the number of tracking pipes in the embedded -TT to four (4) will impose the
restriction that no more than four periodic transactions (INTERRUPT/ISOCHRONOUS) can be
scheduled through the TT per frame. the number 16 was chosen in the USB specification because it
is sufficient to ensure that the high-speed to full-speed periodic pipeline can remain full. keeping the
pipeline full puts no constraint on the number of periodic transactions that can be scheduled in a
frame and the only limit becomes the flight time of the packets on the bus.
Note: There is no data schedule mechanism for these transactions other than the microframe
pipeline. The emulated TT assumes the number of packets scheduled in a frame does not exceed the
frame duration (1 ms) or else undefined behavior might result.
15.11.8 Port Test Mode
Port Test Control mode behaves as described by EHCI. The modes are set using the usb.PORTSC1
[PTC] bit field.
Start-Split: Start periodic transaction. No Handshake (OK)
Complete-Split: Failed to find transaction in queue. Bus Time Out
Complete-Split: Transaction in queue is busy. NYET
Complete-Split: Transaction in queue is complete. Actual Handshake
Table 15-22: USB Handshake Emulation Conditions (Cont’d)
Condition TT Response