User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 451
UG585 (v1.11) September 27, 2016
Chapter 15: USB Host, Device, and OTG Controller
15.12.3 Isochronous (High Speed) Transfer Descriptor (iTD)
The format of a high-speed isochronous transfer descriptor is illustrated in Table 15-25. This
structure is used only for high-speed isochronous endpoints. The iTD’s must be aligned on a 32-byte
boundary.
iTD DWord 0: Next Link Pointer
The first DWord of an iTD is a pointer to the next schedule data structure.
QH
~~X~
Table 15-40 USB Host Queue Head (QH) Descriptor Format
FSTN
~~~X
Table 15-45 USB Host Frame Span Traversal Node
Descriptor (FSTN) Format
Table 15-24: USB Host Transfer Descriptor Type (TYP) Bit Field (Cont’d)
Data Structure
iTD
00
QH
01
siTD
10
FSTN
11
Description
Table 15-25: USB Host Isochronous Transfer Descriptor (iTD) Format
Reference Type 313029282726252423222120191817161514 13 121110 9 8 7 6 5 4 3 2 1 0 DWord
Table 15-26 Next dTD Next Link Pointer 00 TYP T 0
Table 15-27
Transaction Status and Control
Status Transaction 0 Length
IOC
PG * Transaction 0 Offset * 1
Status Transaction 1 Length
IOC
PG * Transaction 1 Offset * 2
Status Transaction 2 Length
IOC
PG * Transaction 2 Offset * 3
Status Transaction 3 Length
IOC
PG * Transaction 3 Offset * 4
Status Transaction 4 Length
IOC
PG * Transaction 4 Offset * 5
Status Transaction 5 Length
IOC
PG * Transaction 5Offset * 6
Status Transaction 6 Length
IOC
PG * Transaction 6 Offset * 7
Status Transaction 7 Length
IOC
PG * Transaction 7 Offset * 8
Table 15-28
Buffer Pointer List
Buffer Pointer (Page 0) EndPt R Device Address 9
Buffer Pointer (Page 1) IO Maximum Packet Size 10
Buffer Pointer (Page 2) reserved Mult 11
Buffer Pointer (Page 3) reserved 12
Buffer Pointer (Page 4) reserved 13
Buffer Pointer (Page 5) reserved 14
Buffer Pointer (Page 6) reserved 15
Host Controller Read/Write Host Controller Read-only
* means these fields may be modified by the Host controller if the IO field indicates an OUT (DWords 1 to 8).
Table 15-26: USB Host iTD DWord 0: Next Link Pointer
Bits Description
31:5 Next Link Pointer. These bits correspond to memory address signals [31:5], respectively. This field
points to another isochronous transaction descriptor (iTD/siTD) or a QH.
4:3 Reserved. Field reserved and should be set to 0.